S29AL016D70TFI020 Spansion Inc., S29AL016D70TFI020 Datasheet - Page 25

• Manufacturer Part Number: S29AL016D70TFI020
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL016D70TFI020

• Memory Size: 16Mbit
• Memory Configuration: 2M X 8 / 1M X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chip Erase Command Sequence
Sector Erase Command Sequence
December 17, 2004 S29AL016D_00_A2
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations.
for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a hardware reset during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
Figure 4
Operations
ing diagrams.
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command.
quirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The system must rewrite the
command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See
the final WE# pulse in the command sequence.
illustrates the algorithm for the erase operation. See the
DQ3: Sector Erase
tables in
P r e l i m i n a r y
AC Characteristics
Write Operation Status
Timer.) The time-out begins from the rising edge of
Table 9
S29AL016D
shows the address and data requirements
for parameters, and to
Table 9
for information on these status bits.
shows the address and data re-
Figure 18
Erase/Program
for tim-
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