HSP50214BVC Intersil, HSP50214BVC Datasheet - Page 54

• Manufacturer Part Number: HSP50214BVC
• Description: IC's, Microprocessor Support
• Manufacturer: Intersil

Specifications of HSP50214BVC

• No. Of Pins: 120
• Mounting Type: Surface Mount
• No. Of Channels: 1
• Package / Case: 120-MQFP

POSITION
POSITION
POSITION
POSITION
POSITION
31-16
14-12
11-10
11-4
BIT
BIT
BIT
N/A
BIT
N/A
BIT
N/A
9-8
7-6
5-4
3-2
1-0
3-0
15
CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION
Q Data Serial Output
Tag Bit
Magnitude Data Serial
Output Tag Bit
Phase Data Serial
Output Tag Bit
Frequency Data Serial
Output Tag Bit
AGC Data Serial
Output Tag Bit
Timing Error Data
Serial Output Tag Bit
Reserved
Output Buffer Mode
FIFO Mode Depth
Threshold
Snapshot Mode
Interval
Snapshot Mode
Number of Samples
FIFO reset
FIFO Strobe
SYNCOUT Strobe
CONTROL WORD 21: BUFFER RAM OUTPUT CONTROL REGISTER (SYNCHRONIZED TO PROCCLK)
(SYNCHRONIZED TO CLKIN OR PROCCLK DEPENDING ON PROGRAMMING IN CONTROL WORD 0)
FUNCTION
FUNCTION
CONTROL WORD 22: BUFFER RAM OUTPUT FIFO RESET (SYNCHRONIZED TO PROCCLK)
FUNCTION
FUNCTION
FUNCTION
CONTROL WORD 23: INCREMENT OUTPUT FIFO (SYNCHRONIZED TO PROCCLK)
54
(See I Data Serial Output Tag selection above).
(See I Data Serial Output Tag selection above).
(See I Data Serial Output Tag selection above).
(See I Data Serial Output Tag selection above).
(See I Data Serial Output Tag selection above).
(See I Data Serial Output Tag selection above).
Reserved.
0- The output buffer operates in snapshot mode.
1- The output buffer operates in FIFO mode.
In FIFO mode, when the FIFO depth reaches this threshold, an interrupt is generated and the READY
flag is asserted. The threshold may be set from 0 to 7. Bit 14 is the MSB. The interrupt is generated when
the FIFO depth reaches the threshold, as the FIFO fills.
In snapshot mode, the interval between snapshots in the output sample times is determined by this 8-
bit binary number, i.e. 256, (2
parameter to 1 less than the desired interval. Bit 11 is the MSB.
In snapshot mode, the number of samples stored each time the snapshot interval counter times out is
equal to the decimal version of this 4-bit number. The range is 1- 8. Bit 3 is the MSB.
A write to this address increments the output FIFO RAM address pointers to READ = 111 and WRITE =
000.
A write to this address increments the output FIFO/buffer to the next sample set.
A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is
synchronized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on the
programming of bit 3 of Control Word 0.
CONTROL WORD 24: SYNCOUT STROBE OUTPUT PIN
(SYNCHRONIZED WITH PROCCLK) (Continued)
HSP50214B
8
), sample time counts between snapshot samples. Program this
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
May 1, 2007
FN4450.4