LT3050EDDB#PBF Linear Technology, LT3050EDDB#PBF Datasheet - Page 16

• Manufacturer Part Number: LT3050EDDB#PBF
• Description: IC ADJ LDO REG 0.6V TO 44.5V 0.1A DFN-12
• Manufacturer: Linear Technology

Specifications of LT3050EDDB#PBF

• Primary Input Voltage: 45V
• Output Voltage Adjustable Range: 0.6V To 44.5V
• Dropout Voltage Vdo: 340mV
• No. Of Pins: 12
• Output Current: 100mA
• Operating Temperature Range: -40°C To +125°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LT3050 Series
OPERATION
External Programmable Current Limit (I
The I
LT3050 output at a ratio of approximately 1:200 (see Block
Diagram). The I
current limit amplifi er. If the output load increases to the
point where it causes the I
the current limit amplifi er takes control of output regula-
tion so that the I
output voltage. The current limit threshold (I
by attaching a resistor (R
This equation is empirically derived and partially compen-
sates for early voltage effects in the I
It is valid for an input voltage range from 0.6V above the
output to 10V above the output. It is valid for output volt-
ages up to 12V. The accuracy of this equation for setting
the resistor value is approximately ±1%. Unit values are
Amps, Volts, and Ohms.
In cases where the IN to OUT voltage exceeds 10V, fold-
back current limit will lower the internal current level limit,
possibly causing it to preempt the external programmable
current limit. See the Internal Current Limit vs V
graph in the Typical Performance Characteristics section.
If the external programmable current limit is not needed,
the I
requires a 10nF decoupling capacitor.
16
R
IMAX
MAX
MAX
pin must be connected to GND. The I
pin is the collector of a PNP which mirrors the
=
119.22 0.894 V
MAX
MAX
−
pin is also the input to the precision
pin clamps at 0.6V, regardless of the
I
LIMIT
IMAX
MAX
•
) from I
OUT
pin voltage to reach 0.6V,
MAX
MAX
MAX
to GND:
current mirror.
LIMIT
Pin)
IN
MAX
) is set
– V
OUT
pin
See the Typical Performance Characteristics section for
additional information.
FAULT Pin Operation
The FAULT pin is an open collector logic pin which asserts
during internal current limit, precision current limit, ther-
mal limit, or a minimum current fault. There is no internal
pull-up on the FAULT pin; an external pull-up resistor is
required. The FAULT pin provides drive for up to 100μA
of pull-down current. Off state logic may be as high as
45V, regardless of the input voltage used. When asserted,
the FAULT pin drive circuitry adds 50μA (nominal) of GND
pin current.
Depending on the I
and OUT capacitance, the FAULT pin may assert during
startup. Consideration should be given to masking the
FAULT signal during startup. The FAULT pin circuitry is
inactive (not asserted) during shutdown and when the
OUT pin is pulled above the IN pin.
Operation in Dropout
The LT3050 contains circuitry which prevents the PNP
output power device from saturating in dropout. This also
keeps the I
accurately, even in dropout. However, this anti-saturation
circuitry becomes less active at lower output currents, so
there is some degradation of current mirror function for
output currents less than 10mA.
MON
, I
MIN
, and I
MIN
capacitance, BYP capacitance,
MAX
current mirrors functioning
3050fa