PIC18F452I/L Microchip Technology, PIC18F452I/L Datasheet - Page 124

• Manufacturer Part Number: PIC18F452I/L
• Description: IC, 8BIT MCU, PIC18F, 40MHZ, LCC-44
• Manufacturer: Microchip Technology

Specifications of PIC18F452I/L

• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Core Size: 8 Bit
• Program Memory Size: 16 KWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18FXX2
14.5
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 14-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 14.5.3.
FIGURE 14-3:
A PWM output (Figure 14-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 14-4:
DS39564C-page 122
Note: 8-bit timer is concatenated with 2-bit internal Q clock or 2
Note:
CCPR1H (Slave)
CCPR1L
Comparator
Duty Cycle Registers
TMR2
TMR2 = PR2
PR2
bits of the prescaler to create 10-bit time-base.
Comparator
PWM Mode
Duty Cycle
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Period
(Note 1)
TMR2 = Duty Cycle
Clear Timer,
CCP1 pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 = PR2
CCP1CON<5:4>
R
S
Q
TRISC<2>
RC2/CCP1
14.5.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPR1L into
14.5.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
cycle = 0%, the CCP1 pin will not be set)
CCPR1H
Note:
Note:
PWM period = (PR2) + 1] • 4 • T
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
PWM Resolution (max)
The Timer2 postscaler (see Section 12.0)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a
different frequency than the PWM output.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
PWM PERIOD
PWM DUTY CYCLE
(TMR2 prescale value)
© 2006 Microchip Technology Inc.
T
OSC
=
• (TMR2 prescale value)
log
-----------------------------bits
log
⎛
⎝
---------------
F
F
PWM
OSC
OSC
2
•
⎞
⎠