STA339BWS13TR STMicroelectronics, STA339BWS13TR Datasheet - Page 50

• Manufacturer Part Number: STA339BWS13TR
• Description: DIG AUDIO SYSTEM, 2-CH, 36POWERSSOP
• Manufacturer: STMicroelectronics

Specifications of STA339BWS13TR

• Svhc: No SVHC (15-Dec-2010)
• No. Of Pins: 36
• Operating Temperature Range: -20°C To +70°C
• Supply Voltage Max: 21.5V
• Supply Voltage Min: 4.5V
• Termination: RoHS Compliant
• Package / Case: PowerSSO
• Interface: I2C
• Interface Type: I2C
• Rohs Compliant: Yes

Register description
6.6.3
6.6.4
6.6.5
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Limiter 2 attack/release rate (addr 0x14)
Limiter 2 attack/release threshold (addr 0x15)
Description
The STA339BWS includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anti-clipping mode or to actively reduce the dynamic range for a better listening
environment such as a night-time listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in
Each channel can be mapped to either limiter or not mapped, meaning that channel will clip
when 0 dBFS is exceeded. Each limiter looks at the present value of each channel that is
mapped to it, selects the maximum absolute value of all these channels, performs the
limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels
in unison.
Figure 18. Basic limiter and volume flow diagram
The limiter attack thresholds are determined by the LxAT registers if EATHx[7] bits are set
to 0 else the thresholds are determined by EATHx[6:0]. It is recommended in anti-clipping
mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of a
FFX amplifier. Since gain can be added digitally within the STA339BWS it is possible to
exceed 0 dBfs or any other LxAT setting, when this occurs, the limiter, when active,
automatically starts reducing the gain. The rate at which the gain is reduced when the attack
threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain
reduction occurs on a peak-detect algorithm. Setting EATHx[7] bits to 1 selects the
anti-clipping mode.
The limiter release thresholds are determined by the LxRT registers if ERTHx[7] bits are set
to 0 else the thresholds are determined by ERTHx[6:0]. Settings to 1 ERTHx[7] bits the
anti-clipping mode is selected automatically. The release of limiter, when the gain is again
increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block
is passed through a RMS filter. The output of this filter is compared to the release threshold,
determined by the Release Threshold register. When the RMS filter output falls below the
L2AT3
L2A3
D7
D7
0
0
L2AT2
L2A2
D6
D6
1
1
GAIN / VOLUME
GAIN / VOLUME
INPUT
INPUT
L2AT1
L2A1
D5
D5
1
1
Doc ID 15276 Rev 3
GAIN
GAIN
L2AT0
L2A0
Configuration register E (addr 0x04) on page
D4
D4
0
0
ATTENUATION
ATTENUATION
LIMITER
LIMITER
+
+
L2RT3
L2R3
D3
D3
1
1
SATURATION
SATURATION
L2RT2
RMS
RMS
L2R2
D2
D2
0
0
OUTPUT
OUTPUT
L2RT1
L2R1
D1
D1
1
0
STA339BWS
L2RT0
L2R0
32.
D0
D0
0
1