DS90C383BMT National Semiconductor, DS90C383BMT Datasheet - Page 4

• Manufacturer Part Number: DS90C383BMT
• Description: IC, LVDS TRANSMITTER, 3.6V, TSSOP-56
• Manufacturer: National Semiconductor

Specifications of DS90C383BMT

• Supply Voltage Range: 3V To 3.6V
• Power Dissipation Pd: 1.63W
• Operating Temperature Range: -10°C To +70°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 56
• Voltage, Vcc: 4V
• Supply Voltage Max: 3.6V
• Rohs Compliant: Yes
• No. Of Drivers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
THTC
TCCD
TPLLS
TPDD
Symbol
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking
Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
SSCG
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note
5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note
5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN (Figure 6 )
TxIN Hold to TxCLK IN (Figure 6 )
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle
input clock is assumed, T
T
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle
input clock is assumed, T
T
Spread Spectrum Clock support; Modulation frequency with a
linear profile(Note 6).
Transmitter Phase Lock Loop Set (Figure 8 )
Transmitter Power Down Delay (Figure 10 )
A
A
= 70˚C,and 25MHz for ” Max ”, V
= 70˚C, and 25MHz for ” Max ”, V
A
A
= −10˚C, and 65MHz for ” Min ”,
= −10˚C, and 65MHz for ” Min ”,
Parameter
CC
CC
= 3.6V, R_FB = V
= 3.6V, R_FB = GND
4
(Continued)
CC
f =
25MHz
f =
40MHz
f =
65MHz
25MHz
f = 40
MHz
f =
−0.25
10.46
14.04
17.61
21.18
−0.45
10.98
16.69
22.41
25.12
33.84
3.340
3.011
3.32
6.89
5.26
Min
2.5
0.5
2.5%/−5%
2.5%/−5%
2.5%/−5%
100kHz
100kHz
100kHz
10.71
14.29
17.86
21.43
11.43
17.14
22.86
28.57
34.29
3.57
7.14
5.71
Typ
0
0
±
±
±
+0.25
+0.45
10.96
14.54
18.11
21.68
11.88
17.59
23.31
29.02
34.74
7.211
6.062
Max
3.82
7.39
6.16
100
10
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns