C8051F380DK Silicon Laboratories Inc, C8051F380DK Datasheet - Page 31
C8051F380DK
Manufacturer Part Number
C8051F380DK
Description
DEV KIT FOR C8051F380
Manufacturer
Silicon Laboratories Inc
Datasheet
1.TOOLSTICK381DC.pdf
(43 pages)
Specifications of C8051F380DK
Processor To Be Evaluated
C8051F380
Processor Series
C8051F38x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-2012
31
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Read: Master Receiver
Transmitted by the SMBus Slave
Transmit mode always interrupts after the ACK/NAK
Start
Received by SMBus Slave
First byte transfer the device is the master transmitter and interrupts after the
ACK
The device then becomes the receiver and generates the interrupt based on
the hardware acknowledgement bit (EHACK)
Slave Address
EHACK = 1 then interrupts occur after the ACK/NAK
EHACK = 0 then interrupts occur before the ACK/NAK period and firmware must
write the desired value to the ACK bit
W
A
Master Read Interrupt Generation
Data Byte
A
Data Byte
N Stop
Interrupts generated
Interrupts generated
with EHACK = 1
with EHACK = 0