C8051F380DK Silicon Laboratories Inc, C8051F380DK Datasheet - Page 26

DEV KIT FOR C8051F380

C8051F380DK

Manufacturer Part Number
C8051F380DK
Description
DEV KIT FOR C8051F380
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F380DK

Processor To Be Evaluated
C8051F380
Processor Series
C8051F38x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-2012
26
SMBus Timing Control
The SMBCS1–0 bits in SMB0CF select the SMBus clock source
Overflows from Timer 0, Timer 1 or Timer 2 set the time-base
Used only when operating as a Master or when the Bus Free Timeout detection
is enabled
Selected clock source may be shared by other peripherals so long as the timer is
left running at all times.
•Example, Timer 1 overflows may generate the SMBus and UART baud rates
simultaneously
Timer overflow rate determines high and low
time and must conform to the standards as
well as the requirements of the system, i.e.
not driven or extended by another device)
T
HIGH
Actual bit rate of the peripheral
typically twice as large as T
bus loading affects timing.
LOW
(SCL

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