RT9218GS Richtek USA Inc, RT9218GS Datasheet - Page 11

• Manufacturer Part Number: RT9218GS
• Description: IC CTRLR PWM SYNC BUCK 14SOP
• Manufacturer: Richtek USA Inc

Specifications of RT9218GS

• Topology: Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 2
• Frequency - Switching: 300kHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 5V, 12V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The AC impedance of output capacitor at operating
frequency is quite smaller than the load impedance, so
the ripple current (ΔI
through output capacitor. The output ripple voltage is
described as :
where ΔV
For electrolytic capacitor application, typically 90 to 95%
of the output voltage ripple is contributed by the ESR of
output capacitor. So Equation (4) could be simplified as :
Users could connect capacitors in parallel to get calculated
ESR.
Input Capacitor
The selection of input capacitor is mainly based on its
maximum ripple current capability. The buck converter
draws pulsewise current from the input capacitor during
the on time of S1 as shown in Figure 1. The RMS value of
ripple current flowing through the input capacitor is
described as :
The input capacitor must be cable of handling this ripple
current. Sometime, for higher efficiency the low ESR
capacitor is necessarily.
PWM Loop Stability
RT9218 is a voltage mode buck converter using the high
gain error amplifier with transconductance (OTA,
Operational Transconductance Amplifier).
The transconductance :
The mid-frequency gain :
DS9218-08 March 2007
dV
G
Δ
Irms
GM
ΔV
ΔV
ΔV
=
OUT
V
OUT
dV
OUT
OUT
OUT
dV
=
=
OUT
=
IN
dI
=
I
dVm
OUT
OR
dI
=
=
=
OUT
Δ
OUT
ΔV
ΔI
ΔI
I
=
is caused by ESR and ΔV
L
L
L
x rc
GMZ
OR
D(1
×
×
Z
rc
OUT
ΔI
+
−
L
OUT
+
L
ΔV
D)
) of the inductor current flows mainly
×
C
=
rc
1
OC
O
GMdV
(A)
+
∫
t1
t2
8
1
ic
V
C
IN
OUT
dt
OL
Z
OUT
(1
−
OC
D)T
by capacitance.
S
2
(2)
(3)
(4)
(5)
(6)
Z
(see Figure 3 and Figure 4),
Figure 3. A Type 2 error-amplifier with shut network to
Pole and Zero :
We can see the open loop gain and the Figure 3 whole
loop gain in Figure 5.
RT9218 internal compensation loop :
OUT
GM = 0.2ms, R1 = 75kΩ, C1 = 2.5nF, C2 = 10pF
F
P
is the shut impedance at the output node to ground
=
2
π
Figure 5. Gain with the Figure 2 circuit
100
ground
×
EA+
EA-
GM
A
1
R
1
F
C
Figure 4. Equivalent circuit
Z
Gain = GMR
1000
2
Frequency (Hz)
+
;
-
F
Z
GM
10k
=
C
R
F
1
P
1
1
2
π
Open Loop, Unloaded Gain
100k
×
Closed Loop, Unloaded Gain
+
1
R
R
B
1
C
C
O
2
1
V
OUT
V
OUT
RT9218
www.richtek.com
11