RT9218GS Richtek USA Inc, RT9218GS Datasheet - Page 10

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RT9218GS

Manufacturer Part Number
RT9218GS
Description
IC CTRLR PWM SYNC BUCK 14SOP
Manufacturer
Richtek USA Inc
Datasheet

Specifications of RT9218GS

Topology
Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
Function
Any Function
Number Of Outputs
2
Frequency - Switching
300kHz
Voltage/current - Output 1
Controller
Voltage/current - Output 2
Controller
W/led Driver
No
W/supervisor
No
W/sequencer
No
Voltage - Supply
5V, 12V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
V
RT9218
Application Information
Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. Low inductance value has smaller size, but
results in low efficiency, large ripple current and high output
ripple voltage. Generally, an inductor that limits the ripple
current (ΔI
appropriate. Figure 1 shows the typical topology of
synchronous step-down converter and its related
waveforms.
Figure 1. The waveforms of synchronous step-down
www.richtek.com
10
IN
i
S1
i
L
i
S1
i
V
S2
L
V
V
L
g1
g2
converter
) between 20% and 50% of output current is
S1
S2
T
ON
ΔI
T
S
T
L
OFF
i
S2
+
V
L
L
-
I
V
L
V
OC
+
+
OR
-
-
r
C
C
V
OUT
i
I
C
- V
L
IN
= I
R
- V
OUT
L
OUT
OUT
I
OUT
V
OUT
+
-
According to Figure 1 the ripple current of inductor can be
calculated as follows :
Where :
V
V
Δt = S1 turn on time
ΔI
f
D = Duty Cycle
r
Output Capacitor
The selection of output capacitor depends on the output
ripple voltage requirement. Practically, the output ripple
voltage is a function of both capacitance value and the
equivalent series resistance (ESR) r
the related waveforms of output capacitor.
S
C
IN
OUT
L
= Switching frequency
= Equivalent series resistor of output capacitor
Figure 2. The related waveforms of output capacitor
L
= Inductor current ripple
V
= Maximum input voltage
IN
=
= Output Voltage
V
V
(V
OC
OR
V
i
i
L
C
IN
0
OUT
0
V
di
dt
=
L
OUT
=
L
V
ΔI
)
IN
Δt
t1
×
L
-V
L
V
; Δt
OUT
IN
×
V
T
fs ΔI
OUT
S
=
t2
×
D
fs
1/2
; D
L
di
dt
DS9218-08 March 2007
ΔI
L
=
L
=
V
V
C
OUT
V
L
OUT
. Figure 2 shows
IN
I
OUT
ΔI
ΔI
ΔV
L
L
x r
OC
c
(1)

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