MC34844AEP Freescale Semiconductor, MC34844AEP Datasheet - Page 57

• Manufacturer Part Number: MC34844AEP
• Description: IC LED DVR BACKLIGHT 10CH 32QFN
• Manufacturer: Freescale Semiconductor

Specifications of MC34844AEP

• Constant Current: Yes
• Internal Driver: Yes
• Type - Primary: Backlight
• Mounting Type: Surface Mount
• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 10
• Frequency: Adjustable/Selectable
• Voltage - Supply: 7 V ~ 28 V
• Voltage - Output: 60V
• Package / Case: 32-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 105°C
• Operating Supply Voltage: 7 V to 28 V
• Maximum Supply Current: 10 mA
• Maximum Power Dissipation: 3.9 W
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RECOMMENDED STACK-UP
up for the signals to have good shielding and Thermal
Dissipation.
DECOUPLING CAPS
the beginning and at the end of any power signal traces to
filter high frequency noise.
end of any long trace to cancel antenna effects on it.
point to be decoupled and the connection to GND should be
as short as possible.
SM-BUS/I
SIGNALS (SDA, SCK AND CK)
power or high frequency signals, it is a good practice to shield
them with ground planes placed on adjacent layers. Make
sure the ground plane is uniform through the whole signal
trace length.
other clock signals in the same routing layer. If they have to
cross or to be routed close to a power signal, it is a good
practice to trace them perpendicularly or at 45° on a different
layer to avoid coupling noise.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Figure 32. Recommended shielding for critical signals.
The following table shows the recommended layer stack-
It is recommended to place decoupling caps of 100 pf at
Decoupling caps of 100 pf should be also placed at the
These caps should be located as closed as possible to the
To avoid contamination of these signals by nearby high
These signals shall not run parallel to power signals or
Table 16. Layer Stacking Recommendations
Layer 1 (Top)
Layer 2 (Inner 1)
Layer 3(Inner 2)
Layer 4 (Bottom)
2
C COMMUNICATION AND CLOCK
DO
Ground Plane
Signal
Stack-Up
Ground
Ground
Signal
Signal
Signal
Ground Planes
LAYOUT GUIDELINES
SWITCHING NODE (SWA & SWB)
as close as possible to each other to keep the switching loop
small enough so that it does not contaminate other signals.
However, care must be taken to ensure the copper traces
used to connect these components together on this node are
capable to handle the necessary current and voltage.
of copper is capable of handling one ampere.
should be as wide and short as possible to avoid adding
inductance or resistance to the loop. The placement of these
components should be selected far away from sensitive
signals like compensation, feedback and internal regulators
to avoid power noise coupling.
COMPENSATION COMPONENTS
close as possible to the pin.
FEEDBACK SIGNAL
perpendicularly or at 45° on a different layer to avoid coupling
noise, preferably between ground or power planes.
The components associated to this node must be placed
As a reference, a 10 mils trace with a thickness of 1.0 oz.
Traces for connecting the inductor, input and output caps
Components related with COMP pin need to be placed as
The trace of the feedback signal (VOUT) should be routed
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Figure 33. Feedback Signal Tracing
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LAYOUT GUIDELINES
On State
Off State
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