PC28F00AP33TFA NUMONYX, PC28F00AP33TFA Datasheet - Page 39

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PC28F00AP33TFA

Manufacturer Part Number
PC28F00AP33TFA
Description
IC FLASH 1GBIT P33 65NM 64EZBGA
Manufacturer
NUMONYX
Series
Axcell™r
Datasheet

Specifications of PC28F00AP33TFA

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1G (64M x 16)
Speed
95ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
904253
904253
PC28F00AP33TF 904253

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PC28F00AP33TFA
Manufacturer:
Micron Technology Inc
Quantity:
10 000
P33-65nm
Table 15: End of Wordline Data and WAIT state Comparison
11.2.4
Table 16: WAIT Functionality Table
11.2.5
11.2.6
Datasheet
41
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Notes:
1.
2.
Latency Count
Active: WAIT is asserted until data becomes valid, then deasserts.
When OE# = V
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
WAIT Polarity (RCR.10)
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (V
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
WAIT Delay (RCR.8)
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
Burst Sequence (RCR.7)
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported.
lengths, as well as the effect of the Burst Wrap (BW) setting.
IH
during writes, WAIT = High-Z.
Not Supported
Not Supported
Condition
Data States
4
4
4
4
4
4
P33-130nm
Table 17
Not Supported
Not Supported
WAIT States
shows the synchronous burst sequence for all burst
0 to 1
0 to 2
0 to 3
0 to 4
0 to 5
0 to 6
High-Z
Active
Active
Active
Deasserted
High-Z
Not Supported
Not Supported
Not Supported
Not Supported
Data States
16
16
16
16
16
16
16
16
16
16
16
WAIT
P33-65nm
Order Number:208043-05
OH
or V
Not Supported
Not Supported
Not Supported
Not Supported
WAIT States
0 to 10
0 to 11
0 to 12
0 to 13
0 to 14
OL
0 to 4
0 to 5
0 to 6
0 to 7
0 to 8
0 to 9
) of WAIT.
Notes
Apr 2010
1,2
1
1
1
1
1

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