A3P030-VQG100 Actel, A3P030-VQG100 Datasheet - Page 57
A3P030-VQG100
Manufacturer Part Number
A3P030-VQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P030-VQG100
Processor Series
A3P030
Core
IP Core
Number Of Programmable I/os
77
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
MICRO
Quantity:
778
Part Number:
A3P030-VQG100
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P030-VQG100I
Manufacturer:
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12 000
Company:
Part Number:
A3P030-VQG100I
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Microsemi SoC
Quantity:
10 000
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Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to
operate at the equivalent software default drive strength. These values are for normal ranges ONLY.
Commercial-Case Conditions: T
Applicable to Standard Plus I/O Banks
Software
Strength
Option
Default
Equiv.
16 mA
Drive
2 mA
6 mA
4 mA
8 mA
1
Speed
Grade
Std.
Std.
Std.
Std.
Std.
–1
–2
–1
–2
–1
–2
–1
–2
–1
–2
t
DOUT
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
11.14 0.04 1.52 0.43
9.48
8.32
6.96
5.92
5.20
6.96
5.92
5.20
4.89
4.16
3.65
4.89
4.16
3.65
t
DP
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
0.04 1.29 0.36
0.03 1.14 0.32
0.04 1.52 0.43
0.04 1.29 0.36
0.03 1.14 0.32
0.04 1.52 0.43
0.04 1.29 0.36
0.03 1.14 0.32
0.04 1.52 0.43
0.04 1.29 0.36
0.03 1.14 0.32
0.04 1.52 0.43
0.04 1.29 0.36
0.03 1.14 0.32
t
DIN
t
R e v i s i o n 9
PY
t
EOUT
Table 2-6 on page 2-6
11.14
9.48
8.32
6.96
5.92
5.20
6.96
5.92
5.20
4.89
4.16
3.65
4.89
4.16
3.65
t
ZL
9.54 3.51 3.61 14.53 12.94
8.12 2.99 3.07 12.36 11.00
7.13 2.62 2.70 10.85 9.66
5.79 3.99 4.45 10.35 9.19
4.93 3.39 3.78 8.81
4.33 2.98 3.32 7.73
5.79 3.99 4.45 10.35 9.19
4.93 3.39 3.78 8.81
4.33 2.98 3.32 7.73
3.92 4.31 4.98 8.28
3.34 3.67 4.24 7.04
2.93 3.22 3.72 6.18
3.92 4.31 4.98 8.28
3.34 3.67 4.24 7.04
2.93 3.22 3.72 6.18
t
ZH
t
LZ
for derating values.
ProASIC3 Flash Family FPGAs
t
HZ
t
ZLS
t
7.82
6.86
7.82
6.86
7.32
6.22
5.46
7.32
6.22
5.46
ZHS
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 43
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