AGLN010V2-UCG36 Actel, AGLN010V2-UCG36 Datasheet - Page 63

• Manufacturer Part Number: AGLN010V2-UCG36
• Description: FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN010V2-UCG36

• Processor Series: AGLN010
• Core: IP Core
• Number Of Macrocells: 86
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 23
• Supply Voltage (max): 1.5 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 10 K
• Package / Case: uCSP-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-16 • Output Enable Register Timing Diagram
Table 2-76 • Output Enable Register Propagation Delays
CLK
D_Enable
Preset
EOUT
Clear
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OECLKQ
OESUD
OEHD
OECLR2Q
OEPRE2Q
OEREMCLR
OERECCLR
OEREMPRE
OERECPRE
OEWCLR
OEWPRE
OECKMPWH
OECKMPWL
For specific junction temperature and voltage supply levels, refer to
Output Enable Register
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width HIGH for the Output Enable Register
Clock Minimum Pulse Width LOW for the Output Enable Register
1.5 V DC Core Voltage
50%
1
50%
t
OESUD
50%
t
OECLKQ
0
t
50%
OEHD
50%
50%
t
OEWPRE
J
t
OEPRE2Q
= 70°C, Worst-Case VCC = 1.425 V
50%
Description
50%
t
50%
R ev i si o n 1 1
OERECPRE
50%
t
t
OEWCLR
OECLR2Q
50%
50%
Table 2-6 on page 2-6
t
50%
OERECCLR
IGLOO nano Low Power Flash FPGAs
50%
t
OECKMPWH
t
OEREMPRE
50%
for derating values.
50%
t
OECKMPWL
0.75
0.51
0.00
1.13
1.13
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std. Units
t
OEREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 49