AGLN010V2-UCG36 Actel, AGLN010V2-UCG36 Datasheet - Page 59

• Manufacturer Part Number: AGLN010V2-UCG36
• Description: FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN010V2-UCG36

• Processor Series: AGLN010
• Core: IP Core
• Number Of Macrocells: 86
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 23
• Supply Voltage (max): 1.5 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 10 K
• Package / Case: uCSP-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-14 • Input Register Timing Diagram
Table 2-72 • Input Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Preset
Out_1
ICLKQ
ISUD
IHD
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
Clear
Data
CLK
For specific junction temperature and voltage supply levels, refer to
Input Register
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
1.5 V DC Core Voltage
50%
1
50%
50%
t
ISUD
0
t
t
ICLKQ
IHD
50%
50%
J
50%
= 70°C, Worst-Case VCC = 1.425 V
t
IWPRE
Description
t
IPRE2Q
50%
50%
R ev i si o n 1 1
t
IRECPRE
t
50%
ICLR2Q
50%
t
IWCLR
50%
50%
50%
Table 2-6 on page 2-6
t
IRECCLR
IGLOO nano Low Power Flash FPGAs
50%
t
ICKMPWH
t
IREMPRE
50%
for derating values.
50%
t
ICKMPWL
0.42
0.47
0.00
0.79
0.79
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
50%
t
50%
IREMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 45