CLC021VGZ-5.0 National Semiconductor, CLC021VGZ-5.0 Datasheet - Page 17

• Manufacturer Part Number: CLC021VGZ-5.0
• Description: IC SERIALIZER VIDEO DGTL 44-PQFP
• Manufacturer: National Semiconductor

Specifications of CLC021VGZ-5.0

• Function: Serializer
• Data Rate: 400Mbps
• Input Type: HCMOS/LSTTL
• Output Type: CMOS, TTL
• Number Of Inputs: 10
• Number Of Outputs: 1
• Voltage - Supply: 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• For Use With: SD021-5EVK - BOARD EVALUATION CLC021AVGZ-5.0
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC021VGZ-5.0

Application Information
PCB LAYOUT AND POWER SYSTEM BYPASS
RECOMMENDATIONS
Circuit board layout and stack-up for the CLC021 should be
designed to provide noise-free power to the device. Good
layout practice also will separate high frequency or high level
inputs and outputs to minimize unwanted stray noise pickup,
feedback and interference. Power system performance may
be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic ca-
pacitance of the PCB power system which improves power
supply filtering, especially at high frequencies, and makes
the value and placement of external bypass capacitors less
critical. External bypass capacitors should include both RF
ceramic and tantalum electrolytic types. RF capacitors may
use values in the range 0.01 µF to 0.1 µF. Tantalum capaci-
tors may be in the range 2.2 µF to 10 µF. Voltage rating for
tantalum capacitors should be at least 5X the power supply
voltage being used. It is recommended practice to use two
vias at each power pin of the CLC021 as well as all RF
bypass capacitor terminals. Dual vias reduce the intercon-
nect inductance by up to half, thereby reducing interconnect
inductance and extending the effective frequency range of
the bypass components.
The outer layers of the PCB may be flooded with additional
V
isolation as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
SS
(ground) plane. These planes will improve shielding and
(Continued)
FIGURE 12. Jitter Plots
17
planes must be tied to the V
quent intervals with vias. Frequent via placement also im-
proves signal integrity on signal transmission lines by pro-
viding short paths for image currents which reduces signal
distortion. The planes should be pulled back from all trans-
mission lines and component mounting pads a distance
equal to the width of the widest transmission line or the
thickness of the dielectric separating the transmission line
from the internal power or ground plane(s) whichever is
greater. Doing so minimizes effects on transmission line
impedances and reduces unwanted parasitic capacitances
at component mounting pads.
In especially noisy power supply environments, such as is
often the case when using switching power supplies, sepa-
rate filtering may be used at the CLC021’s VCO and output
driver power pins. The CLC021 was designed for this situa-
tion. The digital section, VCO and output driver power supply
feeds are independent (see pinout description table and
pinout drawing for details). Supply filtering may take the form
of L-section or pi-section, L-C filters in series with these V
inputs. Such filters are available in a single package from
several manufacturers. Despite being independent feeds, all
device power supplies should be applied simultaneously as
from a common source. The CLC021 is free from power
supply latch-up caused by circuit-induced delays between
the device’s three separate power feed systems.
SS
power supply plane at fre-
10136811
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