DS90UR907QSQX/NOPB National Semiconductor, DS90UR907QSQX/NOPB Datasheet - Page 3

• Manufacturer Part Number: DS90UR907QSQX/NOPB
• Description: IC SERIALIZER 5-65MHZ 24B 36LLP
• Manufacturer: National Semiconductor

Specifications of DS90UR907QSQX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Name
Control and Configuration
PDB
VODSEL
De-Emph
MAPSEL
CONFIG
[1:0]
ID[x]
SCL
SDA
BISTEN
RES[7:0]
FPD-Link II Serial Interface
DOUT+
DOUT-
Power and Ground
VDDL
VDDP
VDDHS
VDDTX
VDDRX
V
GND
DDIO
NOTE: 1 = HIGH, 0 = LOW
The VDD (V
25, 3, 36, 27,
18, 13, 12, 8
DDn
Pin #
10, 9
DAP
and V
23
20
19
26
21
16
15
11
14
17
24
22
4
6
7
5
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise.
I/O, LVCMOS
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
Open Drain
I, LVCMOS
I, LVCMOS
I/O, Type
w/ pull-up
I, Analog
I, Analog
O, LVDS
O, LVDS
Ground
Power
Power
Power
Power
Power
Power
Description
Power-down Mode Input
PDB = 1, Device is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
Differential Driver Output Voltage Select — Pin or Register Control
VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ)
De-Emphasis Control — Pin or Register Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See
FPD-Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on RxIN3+/-.
MAPSEL = 0, LSB on RxIN3+/-.
Operating Modes
Determine the device operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V
Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor V
BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
Reserved - tie LOW
True Output.
The output must be AC Coupled with a 100 nF capacitor.
Inverting Output.
The output must be AC Coupled with a 100 nF capacitor.
Logic Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
TX High Speed Logic Power, 1.8 V ±5%
Output Driver Power, 1.8 V ±5%
RX Power, 1.8 V ±5%
LVCMOS I/O Power and FPD-Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
Table 3
3
Figure 16
Figure 17
DDIO
DDIO
.
.
Table
4.
Table 1
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