DS90UB902QSQE/NOPB National Semiconductor, DS90UB902QSQE/NOPB Datasheet - Page 35

• Manufacturer Part Number: DS90UB902QSQE/NOPB
• Description: IC SER/DESER 10-43MHZ 16B 40-LLP
• Manufacturer: National Semiconductor

Specifications of DS90UB902QSQE/NOPB

• Function: Deserializer
• Data Rate: 688Mbps
• Input Type: CML
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS90UB902QSQE/NOPBTR

Note: AT-SPEED BIST is only available in the Camera mode
and not the Display mode
Step 1: Place the Deserializer in BIST Mode.
Serializer and Deserializer power supply must be supplied.
Enable the AT SPEED BIST mode on the Deserializer by set-
ting the BISTEN pin High. The 902 GPIO[1:0] pins are used
to select the PCLK frequency of the on-chip oscillator for the
BIST test on high speed data path.
The Deserializer GPIO[1:0] set to 00 will bypass the on-chip
oscillator and an external oscillator to Serializer PCLK input
is required. This allows the user to operate BIST under dif-
ferent frequencies other than the predefined ranges.
Step 2: Enable AT SPEED BIST by placing the Serializer into
BIST mode.
Des GPIO
[1:0]
TABLE 5. BIST Oscillator Frequency Select
00
01
10
11
External PCLK
Internal
Internal
Internal
Oscillator
Source
(MHz)
min
10
FIGURE 32. AT-SPEED BIST System Flow Diagram
(MHz)
12.5
typ
50
25
(MHz )
max
43
35
The following diagram shows how to perform system AT
SPEED BIST:
Deserializer will communicate through the bidirectional con-
trol channel to configure Serializer into BIST mode. Once the
BIST mode is set, the Serializer will initiate BIST transmission
to the Deserializer.
Wait 10 ms for Deserializer to acquire lock and then monitor
the LOCK pin transition from LOW to HIGH. At this point, AT
SPEED BIST is operational and the BIST process has begun.
The Serializer will start transfer of an internally generated
PRBS data pattern through the high speed serial link. This
pattern traverses across the interconnecting link to the De-
serializer. Check the status of the PASS pin; a HIGH indicates
a pass, a LOW indicates a fail. A fail will stay LOW for ½ a
clock cycle. If two or more bits in the serial frame fail, the
PASS pin will toggle ½ clock cycle HIGH and ½ clock cycle
low. The user can use the PASS pin to count the number of
fails on the high speed link. In addition, there is a defined SER
and DES register that will keep track of the accumulated error
count. The Serializer 901 GPIO[0] pin will be assigned as a
PASS flag error indicator for the bidirectional control channel
link.
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