DS90UB902QSQE/NOPB National Semiconductor, DS90UB902QSQE/NOPB Datasheet - Page 12

• Manufacturer Part Number: DS90UB902QSQE/NOPB
• Description: IC SER/DESER 10-43MHZ 16B 40-LLP
• Manufacturer: National Semiconductor

Specifications of DS90UB902QSQE/NOPB

• Function: Deserializer
• Data Rate: 688Mbps
• Input Type: CML
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS90UB902QSQE/NOPBTR

www.national.com
t
t
t
t
t
t
t
t
t
t
t
t
t
t
fdev
fmod
RCP
PDC
CLH
CHL
CLH
CHL
ROS
ROH
DD
DDLT
RJIT
RCJ
DPJ
DCCJ
Symbol
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Receiver Output Clock Period
PCLK Duty Cycle
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
Deserializer Delay
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Receiver Clock Jitter
Deserializer Period Jitter
Deserializer Cycle-to-Cycle Clock
Jitter
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
Parameter
t
Default Registers
SSCG[3:0] = OFF
V
3.0V to 3.6V,
C
Default Registers
(Figure
V
3.0V to 3.6V,
C
Default Registers
(Figure
V
3.0V to 3.6V,
C
Default Registers
(Figure
Default Registers
Register 0x03h b[0]
(RRFB = 1)
(Figure
(Figure
(Figure
(Note
PCLK
SSCG[3:0] = OFF
(Note
PCLK
SSCG[3:0] = OFF
(Note
PCLK
SSCG[3:0] = OFF
(Note
LVCMOS Output Bus
SSC[3:0] = ON
(Figure
RCP
DDIO
DDIO
DDIO
L
L
L
= 8 pF (lumped load)
= 8 pF (lumped load)
= 8 pF (lumped load)
= t
: 1.71V to 1.89V or
: 1.71V to 1.89V or
: 1.71V to 1.89V or
Conditions
13,
6,
7,
8,
TCP
14)
14)
16)
15)
13)
17,
20)
Note
Note
Note
Note
Figure
(Note
(Note
(Note
10)
10)
10)
14)
10)
10)
5)
19)
12
PCLK
PCLK
PCLK
ROUT[13:0],
HSYNC, VSYNC
ROUT[13:0],
HSYNC, VSYNC
10 MHz–43 MHz
10 MHz–43 MHz
43 MHz
10 MHz
43 MHz
10 MHz
43 MHz
10 MHz
43 MHz
20 MHz–43 MHz
20 MHz–43 MHz
Pin/Freq.
4.571T
0.38T
0.38T
23.3
Min
1.3
1.3
1.6
1.6
+ 8
45
±0.5% to
9 kHz to
4.571T
66 kHz
±2.0%
0.5T
0.5T
+ 12
0.53
Typ
300
120
425
320
320
300
2.0
2.0
2.4
2.4
50
T
4.571T
+ 16
Max
100
550
250
600
480
500
500
2.8
2.8
3.3
3.3
55
10
Units
kHz
ms
ns
ns
ns
ns
ns
UI
ps
ps
ps
%
%