DS90UB903QSQ/NOPB National Semiconductor, DS90UB903QSQ/NOPB Datasheet - Page 4

• Manufacturer Part Number: DS90UB903QSQ/NOPB
• Description: IC SER/DESER 10-43MHZ 18B 40LLP
• Manufacturer: National Semiconductor

Specifications of DS90UB903QSQ/NOPB

• Function: Serializer
• Data Rate: 900Mbps
• Input Type: LVCMOS
• Output Type: CML
• Number Of Inputs: 1
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.national.com
LVCMOS PARALLEL INTERFACE
DIN[20:0]
PCLK
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0]
BIDIRECTIONAL CONTROL BUS - I
SCL
SDA
MODE
ID[x]
CONTROL AND CONFIGURATION
PDB
RES
FPD-LINK III INTERFACE
DOUT+
DOUT-
POWER AND GROUND
VDDPLL
VDDT
VDDCML
VDDD
VDDIO
VSS
DS90UB903Q Serializer Pin Descriptions
Pin Name
40, 39, 38, 37,
36, 35, 33, 32,
30, 29, 28, 27,
26, 25, 24, 23
22, 21, 20, 19
5, 4, 3, 2, 1,
Pin No.
10, 11
DAP
12
13
17
16
14
15
18
34
31
6
7
8
9
Inputs, LVCMOS
Input, LVCMOS
Input, LVCMOS
Input, LVCMOS
Input, LVCMOS
Power, Analog PLL Power, 1.8V ±5%
Power, Analog Tx Analog Power, 1.8V ±5%
Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%
Power, Digital
Power, Digital
Ground, DAP
Input/Output,
Input/Output,
Input, analog
Input/Output,
Input/Output,
w/ pull down
w/ pull down
w/ pull down
w/ pull down
w/ pull down
Open Drain
Open Drain
I/O, Type
LVCMOS
2
Output,
C COMPATIBLE
CML
CML
Parallel data inputs.
Pixel Clock Input Pin. Strobe edge set by TRFB control register.
General-purpose output pins can be used to control and respond to various
commands.
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to V
Data line for the bidirectional control bus communication
SDA requires an external pull-up resistor to V
I
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Standby mode and is enabled through remote wakeup by Deserializer)
MODE = H, Slave mode; Device accepts SCL clock input and attached to an I
controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Reserved.
This pin MUST be tied LOW.
Non-inverting differential output, bidirectional control channel input. The
interconnect must be AC Coupled with a 100 nF capacitor.
Inverting differential output, bidirectional control channel input. The interconnect
must be AC Coupled with a 100 nF capacitor.
Digital Power, 1.8V ±5%
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from
V
DAP must be grounded. DAP is the large metal contact at the bottom side, located
at the center of the LLP package. Connected to the ground plane (GND) with at
least 16 vias.
2
C Mode select
DDIO
. V
DDIO
can be connected to a 1.8V ±5% or 3.3V ±10%
4
Description
DDIO
DDIO
.
.
Table 3
2
C