DS90UB903QSQ/NOPB National Semiconductor, DS90UB903QSQ/NOPB Datasheet - Page 20

• Manufacturer Part Number: DS90UB903QSQ/NOPB
• Description: IC SER/DESER 10-43MHZ 18B 40LLP
• Manufacturer: National Semiconductor

Specifications of DS90UB903QSQ/NOPB

• Function: Serializer
• Data Rate: 900Mbps
• Input Type: LVCMOS
• Output Type: CML
• Number Of Inputs: 1
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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(Hex)
Addr
TABLE 1. DS90UB903Q Control Registers
A
0
1
2
3
4
5
6
7
8
9
VDDIO Control
I
VDDIO Mode
PCLK_AUTO
I
2
RESERVED
RESERVED
2
C Device ID
C Bus Rate
Reserved
Reserved
I
Reserved
Reserved
Reserved
2
Through
Slave ID
DES ID
C Pass-
Name
Reset
TRFB
Bits
7:1
7:3
7:0
7:6
7:0
7:0
7:1
7:1
7:0
7:0
7:0
0
2
1
0
5
4
3
2
1
0
0
0
Field
DEVICE ID
SER ID SEL
RESERVED
STANDBY
DIGITAL
RESET0
DIGITAL RESET1
RESERVED
RESERVED
VDDIO CONTOL
VDDIO MODE
I
THROUGH
RESERVED
PCLK_AUTO
TRFB
RESERVED
I
DES DEV ID
RESERVED
SLAVE DEV ID
RESERVED
RESERVED
RESERVED
RESERVED
2
2
C PASS-
C BUS RATE
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
20
self clear
self clear
Default
0xB0'h
0xC0'h
0x00'h
0x20'h
0x80'h
0x40'h
0x00'h
0x00'h
0x01'h
0x00'h
11'b
0
0
0
1
1
1
0
1
1
Description
7-bit address of Serializer; 0x58'h
(1011_000X'b) default
0: Device ID is from ID[x]
1: Register I
Reserved
Standby mode control. Retains control register data.
Supported only when MODE = 0
0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1: Disabled. Standby and wake-up disabled
1: Resets the device to default register values. Does not
affect device I
1: Digital Reset, retains all register values
Reserved
Reserved
Auto V
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I
0: Disabled
1: Enabled
Reserved
Switch over to internal 25 MHz Oscillator clock in the
absence of PCLK
0: Disable
1: Enable
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
Reserved
I
f
0x40'h = ~100 kHz SCL (default)
Note: Register values <0x32'h are NOT supported.
Deserializer Device ID = 0x60'h
(1100_000X'b) default
Reserved
Slave Device ID. Sets remote slave I
Reserved
Reserved
Reserved
Reserved
2
2
SCL
C Pass-Through
C SCL frequency is determined by the following:
= 6.25 MHz / Register value (in decimal)
DDIO
detect
2
C Device ID overrides ID[x]
2
C Bus or Device ID
2
C address.