SI3056-FS Silicon Laboratories Inc, SI3056-FS Datasheet - Page 65

• Manufacturer Part Number: SI3056-FS
• Description: IC ISOMODEM DAA SYS-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3056-FS

• Data Format: V.92
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Baud Rates: -

Register 22. Ring Validation Control 1
Reset settings = 1001_0110
Bit
7:6
5:0
Name
Type
Bit
RDLY[1:0]
RMX[5:0]
Name
D7
RDLY[1:0]
R/W
D6
Ring Delay Bits 1 and 0.
These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
0
0
0
.
.
.
1
Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal within a 10% margin of
error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING
event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the
timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then
the frequency of the ring is too high and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/
(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,
f_max], the following equation should be used:
To compensate for error margin and ensure a sufficient ring detection window, it is recom-
mended that the calculated value of RMX[5:0] be incremented by 1.
D5
D4
10
11
01
00
RDLY[1:0]
RMX 5:0
D3
[
RMX[5:0]
] RAS 5:0
Rev. 1.03
≥
R/W
D2
1792
Delay
256
512
0
m
[
s
m
m
m
]
s
s
s
Function
–
D1
-------------------------------------------- - RMX RAS
2 f_max
×
1
×
2 ms
D0
,
Si3018/19/10
≤
65