SI3056-FS Silicon Laboratories Inc, SI3056-FS Datasheet - Page 62

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SI3056-FS

Manufacturer Part Number
SI3056-FS
Description
IC ISOMODEM DAA SYS-SIDE 16SOIC
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI3056-FS

Data Format
V.92
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Baud Rates
-

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Si3018/19/10
Register 18. International Control 3
Reset settings = 0000_0000
62
Name
Bit
7:2
Type
1
0
Bit
Reserved Read returns zero or one.
Reserved Read returns zero or one.
RFWE
Name
D7
Ring Detector Full-Wave Rectifier Enable.
When RNGV (Register 24) is disabled, this bit controls the ring detector mode and the asser-
tion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow
the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect
one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter time-
out of approximately five seconds.
RNGV
0
0
1
1
D6
D5
RFWE
0
1
0
1
D4
D3
Rev. 1.03
Half-Wave
Full-Wave
Validated Ring Envelope
Ring Threshold Crossing One-Shot
RGDT
D2
Function
RFWE
R/W
D1
D0

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