PIC18F24K22-I/ML Microchip Technology, PIC18F24K22-I/ML Datasheet - Page 59

• Manufacturer Part Number: PIC18F24K22-I/ML
• Description: IC PIC MCU 16KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24K22-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
The PIC18(L)F2X/4XK22 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in
Timer
FIGURE 4-1:
 2010 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: See
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
(WDT)”.
RESET
2: PWRT and OST counters are reset by POR and BOR. See Sections
LFINTOSC
Instruction
RESET
OST/PWRT
Pointer
32 s
Stack
( )_IDLE
Brown-out
Time-out
Detect
Table 4-2
Sleep
WDT
Reset
V
DD
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
(2)
for time-out situations.
BOREN
Section 24.2 “Watchdog
(2)
POR
1024 Cycles
65.5 ms
Preliminary
A simplified block diagram of the On-Chip Reset Circuit
is shown in
4.1
Device Reset events are tracked through the RCON
register
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0
Section 4.4 “Brown-out Reset
PIC18(L)F2X/4XK22
RCON Register
(Register
4.3
Figure
“Interrupts”.
and 4.4.
4-1.
4-1). The lower five bits of the
S
R
Registers”.
BOR
(BOR)”.
DS41412D-page 59
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(1)
in