SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 28

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

Si4322
6. Interrupt Handling
In order to achieve low power consumption there is an advanced event handling circuit implemented. The device
has a very low power consumption mode, so called sleep mode. In this mode only a few parts of the circuit are
working. In case of an event, an interrupt signal generated on the nIRQ pin to indicate the changed state to the
microcontroller. If the ewi bit was set in the "5.13. Data Rate Command" on page 24 the device wakes up and
switches into idle mode. The cause of the interrupt can be determined by reading the status word of the device
(see "5.16. Status Register Read Command" on page 26).
Several interrupt sources are available:
FFIT—The number of the received bits in the RX FIFO reached the preprogrammed level: When the number of
received data bits in the receiver FIFO reaches the threshold set by the f5…f0 bits of the "5.14. FIFO Settings
Command" on page 25 and the "5.15. Extended Features Command" on page 26 an interrupt is generated. Valid
only when the fe (enable FIFO mode) bit is set in the FIFO settings command and the receiver is enabled in the
"5.5. Receiver Setting Command" on page 18.
FFOV—FIFO overflow: There are more bits received than the capacity of the FIFO (64 bits). Valid only when the fe
(enable FIFO mode) bit is set in the FIFO settings command and the receiver is enabled in the receiver setting
command.
WKUP—Wake-up timer interrupt: This interrupt event occurs when the time specified by the "5.7. Wake-Up Timer
Command" on page 19 has elapsed. Valid only when the et bit is set in the configuration setting command.
LBD—Low battery detector interrupt: Occurs when the V
threshold level (t3…t0 bits in the "5.10. Low Battery Detector and Microcontroller Clock Divider Command" on page
21). Valid only when the eb (enable low battery detector) bit is set in the configuration setting command.
If an interrupt occurs the nIRQ pin will change to logic low level, and the corresponding bit in the status byte will be
1.
Clearing an interrupt actually implies two things:


To clear an interrupt requires different procedure depending on the interrupt type:
FFIT—Both the nIRQ pin and the status bit remain active until the FIFO is read (a FIFO IT threshold number of bits
have been read), the receiver is switched off, or the RX FIFO is switched off.
FFOV—This bit is always set together with FFIT; it can be cleared by the status read command, but the FFIT bit
and hence the nIRQ pin will remain active until the FIFO is read fully or the RX FIFO is switched off.
WKUP—Both the nIRQ pin and the status bit can be cleared by the Status Read Command
LBD—The nIRQ pin can be released by the reading the status, but the status bit will remain active while the V
below the threshold.
The best practice in interrupt handling is to start with a status read when interrupt occurs, and then make a decision
based on the status byte. It is very important to mention that any interrupt can “wake up” the EZradio chip from
sleep mode if the ewi bit is set in the "5.12. Data Filter Command" on page 23. In this case the crystal oscillator will
start and the Si4322 will not go to low current sleep mode if any interrupt remains active regardless to the state of
the ex (enable crystal oscillator) bit in the "5.3. Configuration Setting Command" on page 16. This way the
microcontroller always can have clock signal to process the interrupt. To prevent high current consumption and this
way short battery life, it is strongly advised to process and clear every interrupt before turning off the crystal
oscillator. All unnecessary functions should be turned off to avoid unwanted interrupts. Before freezing the
microcontroller code, a thorough testing must be performed in order to make sure that all interrupt sources are
handled properly and the part goes to low power consumption (sleep) mode when the crystal oscillator turned off.
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Releasing the nIRQ pin to return to logic high
Clearing the corresponding bit in the status byte
Rev. 1.2
DD
goes below the programmable low battery detector
DD
is