SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 14

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

Si4322
5. Control Interface
Commands to the receiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of
the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial
interface. The number of bits sent is an integer multiple of 8. All commands consist of a command code, followed
by a varying number of parameter or data bits. All data are sent MSB first (e.g., bit 15 for a 16-bit command). Bits
having no influence (don’t care) are indicated with X. Special care must be taken when the microcontroller’s built-in
hardware serial port is used. If the port cannot be switched to 16-bit mode then a separate I/O line should be used
to control the nSEL pin to ensure the low level during the whole duration of the command or a software serial
control interface should be implemented. The Power On Reset (POR) circuit sets default values in all control
registers.
The receiver will generate an interrupt request (IRQ) for the microcontroller on the following events:




FFIT and FFOV are applicable only when the FIFO is enabled. To find out why the nIRQ was issued, the status bits
should be read out.
5.1. Timing Specification
14
Supply voltage below the preprogrammed value is detected (LBD)
Wake-up timer timeout (WK-UP)
FIFO received the preprogrammed amount of bits (FFIT)
FIFO overflow (FFOV)
nSEL
SDO
SCK
SDI
Symbol
t
SS
t
D S
t
t
t
t
t
t
t
t
SHI
OD
CH
SS
SH
DS
DH
CL
BIT15
BIT15
t
C H
t
D H
Select setup time (nSEL falling edge to SCK rising edge)
t
Select hold time (SCK falling edge to nSEL rising edge)
C L
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
BIT 14
BIT14
t
OD
BIT13
BIT 13
Figure 3. Timing Diagram
Select high time
Data delay time
Clock high time
Clock low time
Parameter
Rev. 1.2
BIT8
BIT8
BIT7
BIT7
BIT1
Minimum value [ns]
BIT1
25
25
10
10
25
10
5
5
BIT0
BIT0
t
S H
t
S HI