T4260-ILQ Atmel, T4260-ILQ Datasheet - Page 3

• Manufacturer Part Number: T4260-ILQ
• Description: IC RECEIVER AM/FM FRONT 44-SSOP
• Manufacturer: Atmel

Specifications of T4260-ILQ

• Frequency: AM, FM
• Modulation Or Protocol: AM, FM
• Applications: AM/FM Radio Receiver
• Current - Receiving: 85mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 8 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -

Figure 2. Block Diagram
Functional
Description
4528J–AUDR–11/04
RFAGCFM
RFAGCA1
RFAGCA2
AMAGCO
FMAGCO
MXFMIA
MXFMIB
MXAMIB
MXAMIA
GNDRF
42
12
33
5
7
9
3
4
8
6
AM
AGC
OSCBUF
MXFMOA
22
FM
43
MXFMOB
OSCB
44
21 20 19
MXAMOB
OSCE
39
VCO
OSCGND
DIV
The T4260 implements an AM up-conversion reception path from the RF input signal to
the IF output signal. A VCO and an LO prescaler for AM are integrated to generate the
LO frequency to the AM mixer. The FM reception path generates the same LO
frequency from the RF input signal by a down-conversion to the IF output. The IF A/D
output is designed for digital signal processing. The IF can be chosen in the range of
10 MHz to 25 MHz. Automatic gain control (AGC) circuits are implemented to control the
preamplifier stages in the AM and FM reception paths.
For improved performance, the PLL has an integrated special 2-bit shift fractional logic
with spurious suppression that enables fast frequency changes in AM and FM mode by
a low step frequency (f
Converter) support the alignment via a microcontroller.
For a double-tuner concept, external voltage can be applied at the input of the DACs,
the internal PLL can switched off and the OSC buffer (output) can also be used as input.
Several register bits (bit 0 to bit 145) are used to control the circuit’s operation and to
adapt certain circuit parameters to the specific application. The control bits are orga-
nized in four 8-bit, four 16-bit and three 24-bit registers that can be programmed by the
3-wire bus protocol. The bus protocol and the bit-to-register mapping is described in the
section “3-wire Bus Description” on page 9. The meaning of the control bits is mentioned
in the following sections.
MXAMOA
40
27
REFFREQ
34
IFREF
N DIV
R DIV
IFINAM
35
ININFM
36
PDF
PD
). In addition, two programmable DACs (Digital to Analog
AGC
FMLF
16
17
IFOUTB
AMLF
29 30
IFOUTA
SW-AMLF
18
VTUNE
IFAGCFM
31 10
IFAGCA2
IFAGCA1
32
SUPPLY
RF/IF
PLL
SUPPLY
BUS
14
23
24
25
11
13
15
26
28
37
38
41
2
1
T4260
VRVCO
GNDPLL
VST
GNDT
VSPLL
VRPLL
VRT
SW2/AGC
DATA
DAC2
EN
CLK
SW1
DAC1
3