T4260-ILQ Atmel, T4260-ILQ Datasheet - Page 16

• Manufacturer Part Number: T4260-ILQ
• Description: IC RECEIVER AM/FM FRONT 44-SSOP
• Manufacturer: Atmel

Specifications of T4260-ILQ

• Frequency: AM, FM
• Modulation Or Protocol: AM, FM
• Applications: AM/FM Radio Receiver
• Current - Receiving: 85mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 8 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -

2-bit Shift
SW1 (Pin 13)
16
T4260
If bits 20 and 21 (HCDEL 1) or bits 22 and 23 (HDCEL 2) are both set to 0, then the
high-current charge pump is deactivated. Otherwise, the delay time can be selected as
described in Table 13.
Table 13. Delay Time of HCDEL Register
A divider 2-bit shift (bit 32 = 0) allows faster frequency changes by using a four times
higher step frequency (e.g., f
locked (after the frequency change), the normal step frequency (e.g., f
will be active again.
If no 2-bit shift is used (bit 32 = 1), the frequency changes will be done with the normal
step frequency (12.5 kHz).
In 2-bit shift mode the N- and R-divider are shifted by two bits to the right (this corre-
sponds by a R- and N-divider division by 4). An important condition for this mode is that
the R-divider has to be a multiple of 4.
Table 14. Manual and Lock Detect Shift Mode
The switching output SW1 (pin 13) is controlled by bit 46 as given in Table 15.
Table 15. Switching Output
Note:
Figure 5. Internal Components at SW1
High-current Charge Pump
SW1 is an open-drain output.
Delay time 10 ns
Delay time 15 ns
Delay time 5 ns
OFF
Dividers 2-bit shift
2-bit Shift
SW1
High
Low
No shift
SW1
PDF
= 50 kHz instead of f
B21/B23
0
0
1
1
PDF
= 12.5 kHz). If the PLL is
B46
0
1
B32
0
1
B20/B22
PDF
4528J–AUDR–11/04
0
1
0
1
= 12.5 kHz)