SI4703-B17-GM Silicon Laboratories Inc, SI4703-B17-GM Datasheet - Page 14

• Manufacturer Part Number: SI4703-B17-GM
• Description: IC TUNER FM RADIO RDS/RBDS 20QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4703-B17-GM

• Frequency: 76MHz ~ 108MHz
• Sensitivity: *
• Data Rate - Maximum: *
• Modulation Or Protocol: *
• Applications: *
• Current - Receiving: *
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: *
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: *
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si4703-B17
system performance. To ensure proper performance
and operation, designers should refer to the guidelines
in "AN231: Si4700/01/02/03 Headphone and Antenna
Interface". Conformance to these guidelines will help to
ensure excellent performance even in weak signal or
noisy environments.
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified,
filtered,
analog-to-digital converters (ADCs). This advanced
architecture achieves superior performance by using
digital signal processing (DSP) to perform channel
selection,
processing
architectures.
4.3. General Purpose I/O Pins
The pins GPIO1–3 can serve multiple functions. GPIO1
and GPIO3 can be used to select between 2-wire and
3-wire modes for the control interface as the device is
brought out of reset. See Section “4.9. Reset, Powerup,
and Powerdown”. After powerup of the device, the
GPIO1–3 pins can be used as general purpose inputs/
outputs, and the GPIO2–3 pins can be used as interrupt
request pins for the seek/tune or RDS ready functions
and as a stereo/mono indicator respectively. See
register 04h, bits [5:0] in Section “6. Register
Descriptions” for information on the control of these
pins. It is recommended that the GPIO2–3 pins not be
used as interrupt request outputs until the powerup time
has completed (see Section “4.9. Reset, Powerup, and
Powerdown”). The GPIO3 pin has an internal, 1 M,
±15% pull-down resistor that is only active while RST is
low. General purpose input/output functionality is
available regardless of the state of the V
supplies, or the ENABLE and DISABLE bits.
4.4. RDS/RBDS Processor and
The Si4703 implements an RDS/RBDS* processor for
symbol
detection, and error correction. RDS functionality is
enabled by setting the RDS bit. The device offers two
RDS modes, a standard mode and a verbose mode.
The primary difference is increased visibility to RDS
block-error levels and synchronization status with
verbose mode.
Setting the RDS mode (RDSM) bit low places the
device in standard RDS mode (default). The device will
set the RDS ready (RDSR) bit for a minimum of 40 ms
when a valid RDS group has been received. Setting the
RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 10
will configure GPIO2 to pulse low for a minimum of 5 ms
14
Functionality
decoding,
and
FM
compared
demodulation,
digitized
block
to
with
synchronization,
and
traditional
high
stereo
A
resolution
Confidential Rev. 1.0
and V
analog
audio
error
D
when a valid RDS group has been received. If an invalid
group is received, RDSR will not be set and GPIO2 will
not pulse low. In standard mode RDS synchronization
(RDSS) and block error rate A, B, C and D (BLERA,
BLERB, BLERC, and BLERD) are unused and will read
0. This mode is backward compatible with earlier
firmware revisions.
Setting the RDS mode bit high places the device in RDS
verbose mode. The device sets RDSS high when
synchronized and low when synchronization is lost. If
the device is synchronized, RDS ready (RDSR) will be
set for a minimum of 40 ms when a RDS group has
been received. Setting the RDS interrupt enable
(RDSIEN) bit and GPIO2[1:0] = 10 will configure GPIO2
to pulse low for a minimum of 5 ms if the device is
synchronized and an RDS group has been received.
BLERA,
block-error levels for the RDS group. The number of bit
errors in each block within the group is encoded as
follows: 00 = no errors, 01 = one to two errors, 10 =
three to five errors, 11 = six or more errors. Six or more
errors in a block indicate the block is uncorrectable and
should not be used.
The Si4703 offers an RDS high-performance mode for
RDS-only applications such as TMC (traffic message
channel) coupled with a GPS device. The RDS
performance bit RDSPRF 06h[9] is disabled by default
for backwards compatibility with previous RDS firmware
releases. When RDSPRF is enabled the device
increases
unconditionally remain enabled, and disables FM
impulse detection, thereby avoiding RDS shutdown and
allowing the device to continue to track and decode
RDS in very poor SNR environments.
The Si4703-B17 device possesses an enhanced RDS/
TMC algorithm to improve RDS/TMC reception.
*Note: RDS/RBDS is referred to only as RDS throughout the
4.5. Stereo Audio Processing
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961 and is used worldwide. Today's MPX
signal format consists of left + right (L+R) audio, left –
right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS
data as shown in Figure 8.
remainder of this document.
BLERB,
power
to
BLERC
the
and
LNA,
BLERD
sets
RDS
provide
to