ATA3741P3-TGQY Atmel, ATA3741P3-TGQY Datasheet - Page 15

• Manufacturer Part Number: ATA3741P3-TGQY
• Description: IC UHF ASK/FSK RECEIVER 20SOIC
• Manufacturer: Atmel

Specifications of ATA3741P3-TGQY

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 7mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Frequency (max): 450000kHz
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ATA3741P3-TGQYCT

5.3.2
5.4
5.4.1
Figure 5-8.
4899B–RKE–10/06
Receiving Mode
Clock bit check
counter
Dem_out
DATA
Duration of the Bit Check
Digital Signal Processing
Synchronization of the Demodulator Output
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator
delivers random signals. The bit check is a statistical process and T
Therefore, an average value for T
on the selected baud rate range and on T
T
In the presence of a valid transmitter signal, T
nal, on f
results in a longer period for T
T
If the bit check is successful for all bits specified by N
mode. As seen in
connected microcontroller can be woken up by the negative edge at pin DATA. The receiver
stays in that condition until it is explicitly switched back to polling mode.
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
as a result converted into the output signal data. This processing depends on the selected baud
rate range (BR_Range).
clock cycle T
after T
integral multiple of T
The minimum time period between two edges of the data signal is limited to t
implies an efficient suppression of spikes at the DATA output. At the same time, it limits the max-
imum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller. T
t
following level is frozen for the time period T
T
The maximum time period for DATA to be low is limited to T
finite response time during programming or switching off the receiver via pin DATA. T
is thereby longer than the maximum time period indicated by the transmitter data stream.
5-10 on page 16
to receiving mode.
ee
Bitcheck
Preburst
DATA_min
T
XClk
as illustrated in
XClk
, resulting in lower current consumption in polling mode.
.
Sig
= tmin2 is the relevant stable time period.
elapsed. The edge-to-edge time period t
, and on the count of the checked bits, N
XClk
. This clock is also used for the bit-check counter. Data can change its state only
gives an example where Dem_out remains low after the receiver has switched
DATA_min
Figure 5-3 on page
Figure 5-9 on page
XClk
t
.
ee
Figure 5-8
is to some extent affected by the preceding edge-to-edge time interval
Bitcheck
Bitcheck
illustrates how Dem_out is synchronized by the extended
12, the internal data signal is then switched to pin DATA. A
, requiring a higher value for the transmitter preburst
16. If t
is given in “Electrical Characteristics”. T
Clk
. A higher baud rate range causes a lower value for
DATA_min
ee
Bitcheck
is in between the specified bit-check limits, the
ee
= tmin1; if t
Bitcheck
of the Data signal, as a result, is always an
is dependent on the frequency of that sig-
Bitcheck
. A higher value for N
, the receiver switches to receiving
DATA_L_max
ee
is outside that bit check limit,
Bitcheck
. This function ensures a
varies for each check.
ee
ATA3741
Bitcheck
Bitcheck
T
DATA_min
DATA_L_max
depends
thereby
Figure
. This
15