SI4320-J1-FT Silicon Laboratories Inc, SI4320-J1-FT Datasheet - Page 22

• Manufacturer Part Number: SI4320-J1-FT
• Description: IC RCVR FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4320-J1-FT

• Package / Case: 16-TSSOP
• Frequency: 315MHz, 433MHz, 868MHz, and 915MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK, OOK
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 5.4 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 315 MHz to 915 MHz
• Operating Supply Voltage: 2.2 V to 5.4 V
• Mounting Style: SMD/SMT
• Supply Current: 3 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1627-5

Low Power Duty-Cycle Operation (LPDM)
To use this mode, pin 8 must be connected to VDD. The logic value of pin 8 defines whether the receiver works in Low Power Duty-Cycle
Mode (LPDM) or not. If the value is high (VDD detected), the chip will wake up in every 300 ms. If the value is low (GND detected), then the
chip is continually ON (active). The chip uses the internal wake-up timer and counter for timing the on/off process. This method reduces the
overall current consumption, which should permit approximately 6 months operation from a 1500 mAh battery.
Low Power Duty-Cycle Internal Operations and Timings (Wake-up on Radio)
The wake-up timer event switches on the crystal oscillator, the internal logic waits about 2.25ms. When the oscillator is stable the controller
switches on the synthesizer as well. The receiver monitors the incoming signal strength during this “ON” state of LPDM. If in the next 6ms the
incoming signal strength is above the defined limit (-103dBm if FCS0=0 or -97dBm if FCS0=1), the synthesizer remains switched on for
30.5ms, otherwise it switches itself off after the 6ms operation time. The period time is about 300ms.
Note 1:
Note 2:
RX-TX ALIGNMENT PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to
use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the
output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived
from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be
no offset if the CLK signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the
status byte from the receiver, the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be
disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).
Synthesizer
recognition
Xtal osc.
Pattern
enable
enable
DRSSI
Every detected synchron word restarts the timer, which controls the ‘ON’ state of the receiver.
If the internal Pattern Recognition block is active (decoding the synchron word), then the internal logic does not switch the
synthesizer off until the incoming data is fully processed.
2.25ms
8.25ms
300ms
30.5ms
300ms
Synchron word (2DD4h) received
Start of new cycle
Active
30.5ms
300ms
Si4320
22