SI4320-J1-FT Silicon Laboratories Inc, SI4320-J1-FT Datasheet - Page 20

• Manufacturer Part Number: SI4320-J1-FT
• Description: IC RCVR FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4320-J1-FT

• Package / Case: 16-TSSOP
• Frequency: 315MHz, 433MHz, 868MHz, and 915MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK, OOK
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 5.4 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 315 MHz to 915 MHz
• Operating Supply Voltage: 2.2 V to 5.4 V
• Mounting Style: SMD/SMT
• Supply Current: 3 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1627-5

STANDALONE OPERATION
The chip supports standalone operation, meaning that with preprogrammed (hard wired) parameters, a simple receiver can be built without
an external microcontroller. After the power-up sequence, the status of pin 8 is queried by connecting internally about 10 µA current on it. If
VSS or VDD is detected, the chip turns to standalone mode. In this case 7 pins are used to configure the receiver and 4 digital outputs are
available:
In the standalone mode, a predefined data sequence should be employed which contains preamble, synchron, chip address, and function
control bytes. To allow the control of the outputs, the chip should receive its chip address byte and twice the same function control byte.
The required data flow sequence:
As a minimum preamble, use at least 16 bits.
The structure of the Function Control Byte is shown below. For each output there are two bits assigned to define their mode of operation:
OUT3 / F1 sent out first., OUT0 – OUT3 represent the four digital output pins, F0 - F1 represents the function bits.
Output functions controlled by the function bits, as follows:
Mono-stable mode will be restarted as long as the proper Function Control Byte is received.
Preamble Byte
OUT3
F1
0
0
1
1
F1
AAh
F0
OUT3
0
1
0
1
F0
Synchron Byte
2Dh
Function
No change
Sets output logical low
Sets output logical high
Sets output high in mono-stable mode, cycle time is 100 ms
OUT2
F1
FCS 0
OUT0
OUT2
OUT3
LPDM
FB S 0
OUT1
FB S 1
Chip Address
Byte
D4h
D2h
B4h
B2h
OUT2
F0
1
2
3
4
5
6
7
8
Control Byte
See below
OUT1
Function
F1
16
15
14
13
12
11
10
9
FCS 3
FCS 2
XTL
V DD
V S S
IN1
IN2
FCS 1
OUT1
of Function Control
One’s complement
F0
See below
Byte
OUT0
F1
Control Byte
See below
Function
OUT0
F0
Si4320
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