SAA6588/V2,112 NXP Semiconductors, SAA6588/V2,112 Datasheet - Page 8

• Manufacturer Part Number: SAA6588/V2,112
• Description: IC RDS/RBDS PRE-PROCESSOR 20DIP
• Manufacturer: NXP Semiconductors

Specifications of SAA6588/V2,112

• Function: Pre-Processor
• Frequency: 57kHz
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935261513112; SAA6588N; SAA6588N

Philips Semiconductors
Data processing control
The pre-processor provides different operating modes
selectable via the external I
control performs the pre-selected operating modes and
controls the requested output of the RDS/RBDS
information.
Restart of synchronization mode:
Error correction control mode for synchronization:
RBDS processing mode:
Data available control mode:
2002 Jan 14
The ‘restart synchronization’ (NWSY) control mode
immediately terminates the actual synchronization and
restarts a new synchronization search procedure. The
NWSY flag is automatically reset after the restart of
synchronization by the decoder.
This mode is required for a fast new synchronization on
the RDS/RBDS data from a new transmitter station if the
tuning frequency is changed by the radio set.
Restart of synchronization search is furthermore
automatically carried out if the internal flywheel signals
a loss of synchronization (see Section “Flywheel for
synchronization hold”).
For error correction and identification of valid blocks
during synchronization search, three different modes
are selectable. (SYM1, SYM0, see Table 4).
The pre-processor is suitable for receivers intended for
the European (RDS) as well as for the USA (RBDS)
standard. If RBDS mode is selected via the I
block detection and the error detection and correction
are adjusted to RBDS data processing.
The pre-processor provides three different RDS/RBDS
data output processing modes selectable via the ‘data
available’ control mode: (see also Section “RDS/RBDS
data output” and Table 5).
Standard processing mode: if the decoder is
synchronized and a new block is received (every
26 bits), the actual RDS/RBDS information of the last
two blocks is available with every new received block.
Fast PI search mode: during synchronization search
and if a new A-block is received, the actual RDS/RBDS
information of this or the last two A-blocks respectively
is available with every new received A-block. If the
decoder is synchronized, the standard processing mode
is valid.
RDS/RBDS pre-processor
2
C-bus. The data processing
2
C-bus, the
8
The RDS/RBDS pre-processor provides data output of the
block identification, the RDS/RBDS information words and
error detection and correction status of the last two blocks
as well as signal quality indication and general decoder
status information.
In addition, the decoder controls also the data request from
the external main controller. The pre-processor activates
the ‘data overflow’ status flag DOFL
(see Section “Programming”), if the decoder is
synchronized and a new RDS/RBDS block is received
before the previously processed block was completely
transmitted via I
the interface registers are not updated until reset of the
data overflow flag by reading via the I
RDS/RBDS data output
The decoded RDS/RBDS block information and the
current pre-processor status is available via the I
For synchronization of data request between main
controller and pre-processor the additional data available
output signal is used.
If the decoder has processed new information for the main
controller the data available signal (DAVN) is activated
(LOW) under the following conditions (see also Table 5):
Reduced data request processing mode: if the
decoder is synchronized and two new blocks are
received (every 52 bits), the actual RDS/RBDS
information of the last two blocks is available with every
two new received blocks.
During synchronization search in DAVB mode if a valid
A-block has been detected. This mode can be used for
fast search tuning (detection and comparison of the PI
code contained in the A-block).
During synchronization search in any DAV mode, if two
blocks in correct sequence have been detected
(synchronization criterion).
If the pre-processor is synchronized and in mode DAVA
and DAVB a new block has been processed. This mode
is the standard data processing mode, if the decoder is
synchronized.
If the pre-processor is synchronized and in DAVC mode
two new blocks have been processed.
If the pre-processor is synchronized and in any DAV
mode loss of synchronization is detected (flywheel
counter overflow and resulting restart of
synchronization).
In any DAV mode, if a reset condition caused by
power-on or voltage-drop is detected.
2
C-bus. After detection of data overflow
Product specification
2
C-bus.
SAA6588
2
C-bus.