AD9856AST Analog Devices Inc, AD9856AST Datasheet
AD9856AST
Specifications of AD9856AST
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AD9856AST Summary of contents
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FEATURES Universal low cost modulator solution for communications applications MHz output bandwidth Integrated 12-bit D/A converter Programmable sample rate interpolation filter Programmable reference clock multiplier Internal SIN(x)/x compensation filter >52 dB SFDR @ 40 MHz A OUT ...
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AD9856 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels ........................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 8 Typical Modulated Output Spectral Plots ................................. 8 Typical Single-Tone Output ...
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SPECIFICATIONS ± 5 3.9 kΩ, external reference clock frequency = 10 MHz with REFCLK multiplier enabled at 20×. S SET Table 1. Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier ...
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AD9856 Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width High (t Minimum Clock Pulse Width Low (t Maximum Clock Rise/Fall Time Minimum Data Setup Time ( Minimum Data Hold Time ( Maximum ...
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ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating ...
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AD9856 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TxENABLE Table 3. Pin Function Descriptions Pin No. Mnemonic Pin Function 1 TxENABLE Input Pulse that Synchronizes the Data Stream 2 D11 Input Data (Most Significant Bit) 3 D10 Input Data 4, 10, 21, ...
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Table 4. Functional Block Mode Descriptions Functional Block Mode Description Operating Modes 1. Complex quadrature modulator mode. 2. Single-tone output mode. Input Data Format Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is 12-bit, twos complement. ...
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AD9856 TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL MODULATED OUTPUT SPECTRAL PLOTS RBW 10kHz REF LVL VBW 1kHz –25dBm SWT 12.5s 0 –8 –16 –24 –32 –40 –48 –56 –64 –72 –80 START 0Hz 5MHz/ Figure 3. QPSK at 42 MHz and 2.56 ...
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TYPICAL SINGLE-TONE OUTPUT SPECTRAL PLOTS RBW 3kHz REF LVL VBW 3kHz –5dBm SWT 28s 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 10MHz/ Figure 7. 21 MHz CW Output RBW 3kHz REF LVL VBW 3kHz ...
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AD9856 TYPICAL NARROW-BAND SFDR SPECTRAL PLOTS RBW 100Hz REF LVL VBW 100Hz –5dBm SWT 50s 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 70.1MHz 10kHz/ Figure 11. 70.1 MHz Narrow-Band SFDR, 10 MHz External Clock with ...
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TYPICAL PLOTS OF OUTPUT CONSTELLATIONS TRACE QPSK MEAS TIME 1.5 CONST 300 M /DIV –1.5 –1.9607843757 Figure 15. QPSK, 65 MHz, 2.56 MS/sec TRACE 64QAM MEAS TIME 1 CONST 200 M /DIV –1 –1.3071895838 ...
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AD9856 POWER CONSUMPTION 1600 +V = +3V S CIC = 2 +25°C 1400 HB3 = OFF 1200 HB3 = ON 1000 800 120 140 160 CLOCK SPEED (MHz) Figure 20. Power Consumption vs. Clock Speed; V 1600 1500 HB3 = ...
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SERIAL CONTROL BUS REGISTER Table 5. Serial Control Bus Register Layout Register AD9856 Register Layout Address Bit 7 Bit 6 (hex) 00 SDO LSB Active First 01 CIC Continuous Gain Mode Interpolator Interpolator Rate <5> ...
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AD9856 REGISTER BIT DEFINITIONS Control Bits—Register Address 00h and 01h SDO Active—Register Address 00h, Bit 7. Active high indicates serial port uses dedicated in/out lines. Default low configures serial port as single-line I/O. LSB First—Register Address 00h, Bit 6. Active ...
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THEORY OF OPERATION To gain a general understanding of the functionality of the AD9856 helpful to refer to Figure 23, a block diagram of the device architecture. The following is a general description of the device functionality. Later ...
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AD9856 The sampled carrier is ultimately destined to serve as the input data to the digital-to-analog converter (DAC) integrated on the AD9856. The DAC output spectrum is distorted due to the intrinsic zero-order hold effect associated with DAC-generated signals. This ...
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For continuous-mode input timing, the TxENABLE pin can be thought data input clock running at half the input sample rate (f /2). In addition to synchronization, for contin- W uous mode timing, the TxENABLE input indicates whether ...
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AD9856 TxENABLE D(11:0) I0 INTERNAL I INTERNAL Q TxENABLE D(11:0) I0 INTERNAL I INTERNAL Q TxENABLE I0(11:6) D(11:6) INTERNAL I INTERNAL Q TxENABLE I0(11:9) D(11:9) INTERNAL I INTERNAL Q TxENABLE D(11:0) IN INTERNAL I IN–2 INTERNAL Q QN– ...
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Continuous Mode Input Timing The AD9856 is configured for continuous mode input timing by writing the continuous mode bit true (Logic 1). The continuous mode bit is in register address 01h, Bit 6. The AD9856 must be configured for full-word ...
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AD9856 HALF-BAND FILTERS (HBFS) Before presenting a detailed description of the HBFs, recall that the input data stream is representative of complex data; i.e., two input samples are required to produce one I/Q data pair. The I/Q sample rate is ...
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In applications requiring both a low data rate and a high output sample rate, a third HBF is available (HBF 3). Selecting HBF 3 offers an upsampling ratio of eight (8) instead of four (4). The combined frequency response of ...
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AD9856 0 –30 –60 –90 –120 –150 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW Figure 35. CIC Filter Frequency Response ( HFB 3 Bypassed) 0 –30 –60 –90 –120 –150 0 ...
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DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW Figure 39. CIC Filter Frequency Response ( HBF 3 Selected) 0 –30 –60 –90 –120 –150 0 144 ...
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AD9856 Table 6. CIC Interpolation Filter Insertion Loss Table Default Gain Interpolation Rate (Linear) (dB) 2 1.0000 0.000 3 0.8438 −1.476 4 1.0000 0.000 5 0.9766 −0.206 6 0.8438 −1.476 7 0.6699 −3.480 8 1.0000 0.000 9 0.7119 −2.951 10 ...
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Figure 43 shows the effectiveness of the ISF in correcting for the SINC distortion. The plot includes a graph of the SINC envelope, the ISF response and the SYSTEM response (which is the product of the SINC and ISF responses). ...
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AD9856 load that the AD9856 sees for signals within the filter pass band. For example Ω terminated input/output low-pass filter looks like a 25 Ω load to the AD9856. The output compliance voltage of the AD9856 is −0.5 ...
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At the completion of any communication cycle, the AD9856 serial port controller expects the next eight rising SCLK edges to be the instruction byte of the next communication cycle. All data input to the AD9856 is registered on the rising ...
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AD9856 SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK—Serial Clock The serial clock pin is used to synchronize data to and from the AD9856 and to run the internal state machines. SCLK maximum frequency is 10 MHz. CS —Chip Select Active low ...
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SCLK PRE CS t DSU t t SCLKPWL SCLKPWH SCLK t DHLD SDIO 1ST BIT SYMBOL DEFINITION t CS SETUP TIME PRE t PERIOD OF SERIAL DATA CLOCK SCLK t SERIAL DATA SETUP TIME DSU t SERIAL DATA ...
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AD9856 PROGRAMMING/WRITING THE AD8320/AD8321 CABLE DRIVER AMPLIFIER GAIN CONTROL Programming the gain control register of the AD8320/AD8321 programmable cable driver amplifier can be accomplished via the AD9856 serial port. Four 8-bit registers (one per profile) within the AD9856 store the ...
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UNDERSTANDING AND USING PIN-SELECTABLE MODULATOR PROFILES The AD9856 quadrature digital upconverter is capable of storing four preconfigured modulation modes called profiles that define the following: • Output frequency—32 bits • Interpolation rate—6 bits • Spectral inversion status—1 bit • Bypass ...
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AD9856 The second method requires 144 MHz with MAX externally 2× upsampled input data. The AD9856 is configured for a CIC interpolation rate of 3 while bypassing the 3rd half- band filter. The input I/Q sample rate ...
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J6 PS0 J7 PS1 J5 REFCLKIN R7 50Ω J3 RST RESET TxENABLE P1 1 TxENABLE 1 2 D11 2 3 D10 4 DVDD DVDD 5 GND DGND 3 6 DUT D9 4 ...
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AD9856 Figure 52. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board Layer 1 (Top)—Signal Routing and Ground Plane Figure 53. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board Layer 2—Ground Plane REF CLOCK IN Figure 56. ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range AD9856AST −40° +85° C AD9856/PCB 0.75 1.60 0.60 MAX 0.45 SEATING PLANE 10° 6° 0.20 2° 0.09 VIEW A 7° 3.5 ° 0° 0.08 MAX ...
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AD9856 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00637–0–1/05(C) Rev Page ...