AD607ARS Analog Devices Inc, AD607ARS Datasheet - Page 15

• Manufacturer Part Number: AD607ARS
• Description: IC LIN RCVR IF SUBSYS LP 20-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD607ARS

• Rohs Status: RoHS non-compliant
• Function: Receiver IF Subsystem
• Frequency: 500MHz
• Rf Type: Cellular, GSM, CDMA, TDMA, TETRA
• Secondary Attributes: -8dBm Input Third Order Intercept
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Operating Supply Voltage: 3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

The mixer’s RF input port is differential, that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased; we will generally assume that RFLO is decoupled to ac
ground. The RF port can be modeled as a parallel RC circuit as
shown in Figure 14.
Figure 14. Mixer Port Modeled as a Parallel RC Network;
an Optional Matching Network Is also Shown
The local oscillator (LO) input is internally biased at V
nominal 1000 Ω resistor internally connected from pin LOIP to
VMID. The LO interface includes a preamplifier that minimizes
the drive requirements, thus simplifying the oscillator design
and reducing LO leakage from the RF port. Internally, this
single-sided input is actually differential; the noninverting input
is referenced to Pin VMID. The LO requires a single-sided
drive of ± 50 mV, or –16 dBm in a 50 Ω system.
The mixer’s output passes through both a low-pass filter and a
buffer, which provides an internal differential to single-ended
signal conversion with a bandwidth of approximately 45 MHz.
Its output at Pin MXOP is in the form of a single-ended cur-
rent. This approach eliminates the 6 dB voltage loss of the usual
series termination by replacing it with shunt terminations at
both the input and the output of the filter. The nominal conver-
sion gain is specified for operation into a total IF band-pass
filter (BPF) load of 165 Ω, that is, a 330 Ω filter doubly-termi-
nated as shown in Figure 14. Note that these loads are con-
nected to bias point VMID, which is always at the midpoint of
the supply (that is, V
The conversion gain is measured between the mixer input and
the input of this filter, and varies between 1.5 dB and 26.5 dB
for a 165 Ω load impedance. Using filters of higher impedance,
the conversion gain can always be maintained at its specified
value or made even higher; for filters of lower impedance, of say
Z
Thus, the use of a 50 Ω filter will result in a conversion gain that
is 5.2 dB lower. Figure 15 shows filter matching networks and
Table I lists resistor values.
Figure 15. Suggested IF Filter Matching Network. The
Values of R1 and R2 Are Selected to Keep the Impedance
at Pin MXOP at 165 Ω
REV. C
O
, the conversion gain will be lowered by 10 log
MXOP
VMID
C1, C2, L1: OPTIONAL MATCHING CIRCUIT
C3: COUPLES RFLO TO AC GROUND
8
9
C1
P
L1
/2).
R1
R2
C3
C2
100nF
BPF
RFHI
RFLO
R3
100nF
AD607
1nF
C
IN
10
11
IFHI
IFLO
R
IN
10
(165/Z
P
/2 via a
O
).
–15–
IF
450 kHz
455 kHz
6.5 MHz
10.7 MHz
*Resistor values were calculated such that R1+ R2 = Z
The maximum permissible signal level at MXOP is determined
by both voltage and current limitations. Using a 3 V supply and
VMID at 1.5 V, the maximum swing is about ± 1.3 V. To attain
a voltage swing of ± 1 V in the standard IF filter load of 165 Ω
requires a peak drive current of about ± 6 mA, which is well
within the linear capability of the mixer. However, these upper
limits for voltage and current should not be confused with issues
related to the mixer gain, already discussed. In an operational
system, the AGC voltage will determine the mixer gain, and
hence the signal level at the IF input Pin IFHI; it will always be
less than ± 56 mV (–15 dBm into 50 Ω), which is the limit of the
IF amplifier’s linear range.
IF Amplifier
Most of the gain in the AD607 arises in the IF amplifier strip,
which comprises four stages. The first three are fully differential
and each has a gain span of 25 dB for the nominal AGC voltage
range. Thus, in conjunction with the mixer’s variable gain, the
total gain exceeds 90 dB. The final IF stage has a fixed gain of
20 dB, and it also provides differential to single-ended conversion.
The IF input is differential, at IFHI (noninverting relative to the
output IFOP) and IFLO (inverting). Figure 16 shows a simpli-
fied schematic of the IF interface. The offset voltage of this
stage would cause a large dc output error at high gain, so it is
nulled by a low pass feedback path from the IF output, also
shown in TPC 13. Unlike the mixer output, the signal at IFOP
is a low-impedance single-sided voltage, centered at V
dc feedback loop. It may be loaded by a resistance as low as
50 Ω, which will normally be connected to VMID.
R1 (R2 + Z
Table I. Filter Termination Resistor Values for
Common IFs
Figure 16. Simplified Schematic of the IF Interface
FILTER
Filter
Impedance
1500 Ω
1500 Ω
1000 Ω
330 Ω
) = 165 Ω.
IFLO
IFHI
OFFSET FEEDBACK
LOOP
Filter Termination Resistor
Values
R1
174 Ω
174 Ω
215 Ω
330 Ω
10k
10k
*
for 24 dB of Mixer Gain
AD607
VMID
R2
1330 Ω
1330 Ω
787 Ω
0 Ω
FILTER
IFOP
and
AD607
P
/2 by the
R3
1500 Ω
1500 Ω
1000 Ω
330 Ω