HSP50415EVAL1 Intersil, HSP50415EVAL1 Datasheet - Page 17

• Manufacturer Part Number: HSP50415EVAL1
• Description: EVALUATION BOARD HSP50415VI
• Manufacturer: Intersil
• Type: Modulator, Demodulatorr

Specifications of HSP50415EVAL1

• For Use With/related Products: HSP50415
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

by performing three (3) 24-bit master to slave loads. Table 9
demonstrates the sequence of writes necessary to load
memory location 0 of the I and Q channel coefficient RAMs
simultaneously.
If auto-increment address mode had been enabled, then the
write to MasterReg<31:24> with the destination memory
address would not have been required, as writing to Control
Word 0 would reset the internal auto-increment address to 0.
Writing a 0x0F to address 4 generates an internal
memUpdate signal that loads the memory buffer from
ADDR<2:0>
ADDR<2:0>
0
4
0
1
2
4
0
1
2
4
0
1
2
3
4
0
4
2
3
4
0x0C
0x00
memData[0][7:0]
memData[0][15:8]
memData[0][23:16]
0x0F
memData[0][31:24]
memData[0][39:32]
memData[0][47:40]
0x0F
memData[0][55:48]
memData[0][63:56]
memData[0][71:64]
0x00 (memAddr)
0x0F
0x10
0x00
memData[0][7:0]
0x00 (memAddr)
0x0F
CDATA<7:0>
CDATA<7:0>
TABLE 10. EXAMPLE SEQUENCE OF WRITES TO LOAD CONSTELLATION MAP RAM
TABLE 9. EXAMPLE SEQUENCE OF WRITES TO LOAD I/Q COEFFICIENT RAM
17
CE
0
0
0
0
0
CE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RD
RD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
HSP50415
1
1
1
1
1
WR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
WR
write to MasterReg<7:0>
MasterReg<7:0> -> cntlWord0<7:0>
write to MasterReg<7:0>
write to MasterReg<15:8>
write to MasterReg<23:16>
MasterReg<23:0> -> memBuf<23:0>
write to MasterReg<7:0>
write to MasterReg<15:8>
write to MasterReg<23:16>
MasterReg<23:0> -> memBuf<47:24>
write to MasterReg<7:0>
write to MasterReg<15:8>
write to MasterReg<23:16>
write to MasterReg<31:24>
MasterReg<23:0> -> memBuf<71:48>
MasterReg<31:24> -> memAddr<7:0>
write to MasterReg<7:0>
MasterReg<7:0> -> cntlWord0<7:0>
write to MasterReg<23:16>
write to MasterReg<31:24>
MasterReg<23:16> -> memBuf<71:64>
MasterReg<31:24> -> memAddr<7:0>
MasterReg<23:0>. Which section of the memory buffer gets
the data is dependent on the memory word select counter
shown in column 7 of Table 9. A memUpdate strobe
increments the word select counter as well as updating the
memBuffer. When the word select counter is equal to 2 and
a memUpdate strobe occurs, memBuf<71:0> data is written
to memAddr<7:0> of the I/Q coefficient RAMs and the mem
word select counter is cleared ready for the next sequence
of writes to the memory buffer. Writing to the constellation
map RAM is much simpler as Table 10 demonstrates.
INTERNAL OPERATION
INTERNAL OPERATION
SELECT<1:0>
SELECT<1:0>
MEM WORD
MEM WORD
00
00
00
00
00
xx
April 23, 2007
00
00
00
00
00
01
01
01
01
10
10
10
10
10
10
xx
FN4559.6