ATA557001-DDW Atmel, ATA557001-DDW Datasheet - Page 4

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ATA557001-DDW

Manufacturer Part Number
ATA557001-DDW
Description
IC IDIC RW RF 125KHZ 330BIT
Manufacturer
Atmel
Datasheet

Specifications of ATA557001-DDW

Function
Read/Write
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4.4
4.5
4.6
4.7
4.8
4.9
4
HV Generator
DC Supply
Power-On Reset (POR)
Clock Extraction
Controller
Mode Register
ATA5570 [Preliminary]
This on-chip charge-pump circuit generates the high voltage required for programming of the
EEPROM.
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regu-
lates this RF source and uses it to generate its supply voltage.
This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached.
The clock extraction circuit uses the external RF signal as its internal clock source.
The control-logic module executes the following functions:
The mode register stores the configuration data from the EEPROM block 0. It is continually
refreshed at the start of every block read and (re-)loaded after any POR event or reset com-
mand. On delivery, the mode register is preprogrammed with the value 0014 8000h which
corresponds to continuous read of block 0, Manchester coded, RF/64.
• Load-mode register with configuration data from EEPROM block 0 after power-on and also
• Control memory access (read, write)
• Handle write data transmission and write error modes
• The first two bits of the reader-to-tag data stream are the opcode, e.g., write, direct access or
• In password mode, the 32 bits received after the opcode are compared with the password
during reading
reset
stored in memory block 7
4863A–RFID–07/05

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