ATA557001-DDW Atmel, ATA557001-DDW Datasheet - Page 11

• Manufacturer Part Number: ATA557001-DDW
• Description: IC IDIC RW RF 125KHZ 330BIT
• Manufacturer: Atmel

Specifications of ATA557001-DDW

• Function: Read/Write
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.8
Figure 5-5.
4863A–RFID–07/05
Write-data Protocol
POR
Block 0 loading
Complete Writing Sequence
Table 5-1.
The ATA5570 expects to receive a dual-bit opcode as the first two bits of a reader command
sequence. There are three valid opcodes:
Writing has to follow these rules:
Note:
If the transmitted command sequence is invalid, the ATA5570 enters regular-read mode with the
previously selected page (by former opcode “10” or “11”).
Parameters
Start gap
Write gap
Write data in normal mode
• The opcodes “10” and “11” precede all block-write and direct-access operations for page 0
• The RESET opcode “00” initiates a POR cycle
• The opcode “01” precedes all test-mode write operations. Any test-mode access is ignored
• Standard write needs the opcode, the lock bit, 32 data bits and the 3-bit address
• Protected write (PWD bit set) requires a valid 32-bit password after opcode and before data
• For the AOR wake-up command an opcode and a valid password are necessary to select
and page 1
after the master key (bits 1 to 4) in block 0 has been set to “6”. Any further modifications of
the master key are prohibited by setting the lock bit of block 0 or the OTP bit.
(38 bits total)
and address bits
and activate a specific tag
Read mode
Start gap
The data bits are read in the same order as written.
Write-data Decoding Scheme
Op-code
Lock bit
Normal write mode
Block data
Remark
“0” data
“1” data
–
Write mode
Block address
ATA5570 [Preliminary]
Symbol
Wgap
Sgap
d0
d1
Programming
Min
10
16
48
8
Max
Read mode
50
30
31
63
Unit
FC
FC
FC
FC
11