ESD3V3U1U-02LRH E6327 Infineon Technologies, ESD3V3U1U-02LRH E6327 Datasheet - Page 5

• Manufacturer Part Number: ESD3V3U1U-02LRH E6327
• Description: DIODE TVS 3.3V TSLP-2-7
• Manufacturer: Infineon Technologies

Specifications of ESD3V3U1U-02LRH E6327

• Package / Case: TSLP-2-7
• Voltage - Reverse Standoff (typ): 3.3V
• Voltage - Breakdown: 5V
• Polarization: Unidirectional
• Mounting Type: Surface Mount
• Applications: General Purpose
• Number Of Circuits: 1
• Voltage - Working: 3.300V
• Technology: Diode Array
• Polarity: Unidirectional
• Clamping Voltage: 15 V
• Operating Voltage: 3.3 V
• Breakdown Voltage: 5 V
• Peak Surge Current: 3 A
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Dimensions: 0.6 mm W x 1 mm L
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Voltage - Clamping: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 3V3U1U02LRHE6327XT; ESD3V3U1U-02LRHE6327INTR; SP000390728

List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Final Data Sheet
Pin Configuration and Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Definitions of Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Line capacitance
Line capacitance
Line capacitance
Reverse current
Clamping voltage
Forward clamping voltage
Single line, uni-directional ESD / Transient
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PG-TSSLP-2-1: Package overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PG-TSSLP-2-1: Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PG-TSSLP-2-1: Packing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PG-TSSLP-2-1: Marking (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PG-TSLP-2-7: Package overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PG-TSLP-2-7: Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PG-TSLP-2-7: Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PG-TSLP-2-7: Marking (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
I
R
C
C
C
V
=
L
L
L
TLP
f(T
=
=
=
f(V
f(f)
f(T
=
A
f(I
)
A
R
, from pin 1 to pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
)
,
) f =
TLP
, from pin 1 to pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
V
V
TLP
R
), from pin 1 to pin
=3.3
1MHz, from pin 1 to pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
=
f(I
V,
TLP
from pin 1 to pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
) , from pin 2 to pin
5
protection[2]
2[1]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1[1]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision 1.0, 2011-04-12
ESD3V3U1U Series
List of Figures