AD8099ARDZ Analog Devices Inc, AD8099ARDZ Datasheet - Page 21

• Manufacturer Part Number: AD8099ARDZ
• Description: IC OPAMP VF ULN ULDIST 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8099ARDZ

• Slew Rate: 1350 V/µs
• Amplifier Type: Voltage Feedback
• Number Of Circuits: 1
• -3db Bandwidth: 510MHz
• Current - Input Bias: 6µA
• Voltage - Input Offset: 100µV
• Current - Supply: 15mA
• Current - Output / Channel: 178mA
• Voltage - Supply, Single/dual (±): 5 V ~ 12 V, ±2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width) Exposed Pad, 8-eSOIC. 8-HSOIC
• Op Amp Type: High Speed
• No. Of Amplifiers: 1
• Bandwidth: 3.8GHz
• Supply Voltage Range: 5V To 12V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

In applications where noise sensitivity is critical, care must be
taken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be
seen in Table 4.
INPUT BIAS CURRENT AND DC OFFSET
In high noise gain configurations, the effects of output offset
voltage can be significant, even with low input bias currents and
input offset voltages. Figure 70 shows a comprehensive offset
voltage model, which can be used to determine the referred to
output (RTO) offset voltage of the amplifier or referred to input
(RTI) offset voltage.
B
A
OFFSET (RTI) = V
OFFSET (RTI) = V
OFFSET (RTO) = V
B
A
V
V
4kTR1
4kTR3
N, R1
N, R3
RTI NOISE =
RTO NOISE = NG × RTI NOISE
FOR BIAS CURRENT CANCELLATION:
R1
R3
Figure 70. Op Amp Total Offset Voltage Model
R1
R3
Figure 69. Op Amp Noise Analysis Model
OS
OS
OS
+ I
I
I
N–
N+
I
1 + R2 + I
B+
I
B–
B+
IF I
+
× R3 – I
V
I
R1
B+
V
N+
N
OS
2
2
V
= I
R3
+ 4kTR3 + 4kTR1
N
B–
V
4kTR2
2
B+
B–
N, R2
+ I
AND R3 = R1 × R2
× R3 1 + R2 – I
N–
R1 × R2
R1 + R2
2
R1 × R2
R1 + R2
R2
R2
R1
R1 + R2
R1 + R2
"B" TO OUTPUT
2
"B" TO OUTPUT
R2
GAIN FROM
+ 4kTR2
B–
GAIN FROM
"A" TO OUTPUT
× R2
"A" TO OUTPUT
GAIN FROM
GAIN FROM
2
NOISE GAIN =
V
OUT
NOISE GAIN =
V
NG = 1 +
OUT
NG = 1 + R2
R1 + R2
R1
= –
= – R2
R2
R1
R2
R1
R1
R1
=
2
=
Rev. B | Page 21 of 28
For RTO calculations, the input offset voltage and the voltage
generated by the bias current flowing through R3 are multiplied
by the noise gain of the amplifier. The voltage generated by I
through R2 is summed together with the previous offset
voltages to arrive at a final output offset voltage. The offset
voltage can also be referred to the input (RTI) by dividing the
calculated output offset voltage by the noise gain.
As seen in Figure 70 if I
parallel combination of R1 and R2, then the RTI offset voltage
can be reduced to only V
reduce output offset voltage. Keeping resistances low helps to
minimize offset error voltage and keeps the voltage noise low.
DISABLE PIN AND INPUT BIAS CANCELLATION
The AD8099 DISABLE pin performs three functions; enable,
disable, and reduction of the input bias current. When the
DISABLE pin is brought to within 0.7 V of the positive supply,
the input bias current is reduced by an approximate factor of 60.
However, the input current noise doubles to 5.2 pA/√ Hz . Table
5 outlines the DISABLE pin functionality.
Table 5. DISABLE Pin Truth Table
Supply Voltage
Disable
Enable
Low Input Bias Current
B+
OS.
and I
This is a common method used to
B–
are the same and R3 equals the
±5 V
–5 to +2.4
Open
4.3 to 5
+5 V
0 to 2.4
Open
4.3 to 5
AD8099
B–