AD8369ARUZ Analog Devices Inc, AD8369ARUZ Datasheet - Page 15

• Manufacturer Part Number: AD8369ARUZ
• Description: IC AMP VGA 16TSSOP
• Manufacturer: Analog Devices Inc
• Series: X-AMP®r

Specifications of AD8369ARUZ

• Amplifier Type: Variable Gain
• Number Of Circuits: 1
• Slew Rate: 1200 V/µs
• -3db Bandwidth: 600MHz
• Current - Input Bias: 160µA
• Current - Supply: 37mA
• Voltage - Supply, Single/dual (±): 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• No. Of Amplifiers: 1
• Bandwidth: 380MHz
• Gain Accuracy: 0.05dB
• No. Of Channels: 1
• Supply Voltage Range: 3V To 5.5V
• Amplifier Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Current - Output / Channel: -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

BASIC CONNECTIONS
Figure 3 shows the minimum connections required for basic
operation of the AD8369. Supply voltages of between +3 V and
+5.5 V are permissible. The supply to the VPOS pin should be
decoupled with at least one low inductance surface-mount ceramic
capacitor of 0.1 mF placed as close as possible to the device. More
effective decoupling is provided by placing a 100 pF capacitor in
parallel and including a 4.7 W resistor in series with the supply.
Attention should be paid to voltage drops. A ferrite bead is a
better choice than the resistor where a smaller drop is required.
Input-Output Interface
A broadband 50 W input termination can be achieved by
using a 1:2 turns-ratio transformer, as shown in Figure 3.
This also can be used to convert a single-ended input signal
to a balanced differential form at the inputs of the AD8369.
As in all high frequency applications, the trace impedance
should be maintained right up to the input pins by careful
design of the PC board traces, as described in the PCB
Layout Considerations section.
Reducing Gain Sensitivity to Input and Output Impedance
Variation
The lot-to-lot variations in gain mentioned previously can, in
principle, be eliminated by adjustments to the source and load.
Define a term
of the AD8369 and the source and load resistances presented to it:
For a 50 W source,
sensitivity to variations must be 800 W. Put more simply:
REV. 0
(
R
SOURCE
as a function of the input and output resistances
) (
R
LOAD
= 0.25. Then the load resistance for zero
R
R
SOURCE
OUTPUT
)
IN
=
(
R
=
=
INPUT
a
a
50 TX LINE
(
(
R
R
INPUT
LOAD
) (
R
OUTPUT
)
)
TC4-1W
)
= 200
3V TO 5.5V
Figure 3. Basic Connections
0.1 F
0.1 F
2
INLO
INHI COMM
V
16
S
1
R
L
COMM BIT0
15
0.1 F
2
–15–
PWUP VPOS SENB
14
3
In general, there is a loss factor, 1/(1+ ), at each interface so
the overall gain reduction due to source and output loading is
40 log
are 0.8 (1.94 dB) at each interface so the overall gain is
reduced by 3.88 dB.
Operation from a Single-Sided Source
While there are distinct benefits of driving the AD8369 with a
well-balanced input, in terms of distortion and gain conform-
ance at high frequencies, satisfactory operation will often be
possible when a single-sided source is ac-coupled directly to pin
INHI, and pin INLO is ac-grounded via a second capacitor. This
mode of operation takes advantage of the good HF common-mode
rejection of the input system. The capacitor values are, as always,
selected to ensure adequate transmission at low frequencies.
SOURCE
Figure 4. Single-Ended-to-Differential Application Example
BIT1
AD8369
13
4
50
10
BIT2
(1 + ). In this case, the input and output loss factors
12
5
0.1 F
0.1 F
0.1 F
BIT3
FILT CMDC OPHI
11
6
0.1 F
INLO
INHI COMM
V
16
1
S
DENB
CONTROL INTERFACE
10
7
COMM BIT0
15
OPLO
2
0.1 F
8
9
PWUP VPOS SENB
14
0.1 F
3
0.1 F
AD8369
BIT1
13
4
R
L
BIT2
12
5
0.1 F
BIT3
FILT CMDC OPHI
11
6
0.1 F
DENB
CONTROL INTERFACE
AD8369
10
7
OPLO
9
8
0.1 F
0.1 F
R
L