C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 225

• Manufacturer Part Number: C8051F321
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

19.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may oper-
ate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or USB Start-of-Frame (SOF) capture mode. The
Timer 2 operation mode is defined by the T2SPLIT (TMR2CN.3) and T2SOF (TMR2CN.4) bits.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided
by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the internal oscillator drives the
system clock while Timer 2 (and/or the PCA) is clocked by an external precision oscillator. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
19.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT = ‘0’ and T2SOF = ‘0’, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be clocked
by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the 16-bit timer register
increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2 reload registers (TMR2RLH and
TMR2RLL) is loaded into the Timer 2 register as shown in Figure 19.11, and the Timer 2 High Byte Overflow Flag
(TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is set), an interrupt will be generated on each Timer 2
overflow. Additionally, if Timer 2 interrupts are enabled and the TF2LEN bit is set (TMR2CN.5), an interrupt will be
generated each time the lower 8 bits (TMR2L) overflow from 0xFF to 0x00.
External Clock / 8
SYSCLK / 12
SYSCLK
T2XCLK
0
1
Figure 19.11. Timer 2 16-Bit Mode Block Diagram
M
T
H
3
M
T
3
L
CKCON
M
H
T
2
M
T
0
1
2
L
M
T
1
M
T
0
S
C
A
1
C
S
A
0
TR2
TCLK
Overflow
TL2
TMR2RLL TMR2RLH
TMR2L
Rev. 1.1
To SMBus
TMR2H
Reload
To ADC,
SMBus
T2SPLIT
TF2LEN
T2XCLK
T2SOF
TF2H
TF2L
TR2
C8051F320/1
Interrupt
225