C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 101

• Manufacturer Part Number: C8051F321
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.2. Power-Fail Reset / VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below V
drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 10.2). When VDD returns to a level above
V
altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data reten-
tion. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD monitor is enabled after power-on resets;
however its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor
is enabled and a software reset is performed, the VDD monitor will still be enabled after the reset.
Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the VDD moni-
tor as a reset source before it is enabled and stabilized will cause a system reset. The procedure for configuring the
VDD monitor as a reset source is shown below:
See Figure 10.2 for VDD monitor timing. See Table 10.1 for complete electrical characteristics of the VDD monitor.
RST
Bit7:
Bit6:
Bits5-0:
VDMEN VDDSTAT Reserved
, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not
R/W
Bit7
Step 1. Enable the VDD monitor (VDM0CN.7 = ‘1’).
Step 2. Wait for the VDD monitor to stabilize (see Table 10.1 for the VDD Monitor turn-on time).
Step 3. Select the VDD monitor as a reset source (RSTSRC.1 = ‘1’).
VDMEN: VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until
it is also selected as a reset source in register RSTSRC (Figure 10.4). The VDD Monitor must be
allowed to stabilize before it is selected as a reset source. Selecting the VDD monitor as a reset
source before it has stabilized will generate a system reset. See Table 10.1 for the minimum VDD
Monitor turn-on time. The VDD Monitor is enabled following all POR resets.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
VDDSTAT: VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
Reserved. Read = Variable. Write = don’t care.
Bit6
R
Figure 10.3. VDM0CN: VDD Monitor Control
Bit5
R
Reserved
Bit4
R
Reserved
Bit3
R
Rev. 1.1
Reserved
Bit2
R
Reserved
Bit1
RST
R
, the power supply monitor will
C8051F320/1
Reserved
Bit0
R
SFR Address:
Reset Value
Variable
0xFF
101