N80C196NT Intel, N80C196NT Datasheet - Page 5

• Manufacturer Part Number: N80C196NT
• Description: IC MPU 16-BIT 5V 20MHZ 68-PLCC
• Manufacturer: Intel
• Series: 80Cr

Specifications of N80C196NT

• Rohs Status: RoHS non-compliant
• Core Processor: MCS 96
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, SSIO
• Peripherals: WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Eeprom Size: -
• Program Memory Size: -
• Other names: 804261

PIN DESCRIPTIONS
V
V
V
V
ANGND
XTAL1
XTAL2
P2 7 CLKOUT
RESET
P5 7 BUSWIDTH
NMI
P5 1 INST SLPCS
EA
HOLD
HLDA
BREQ
P5 0 ALE ADV
SLPADDR
SLPALE
P5 3 RD SLPRD
CC
SS
REF
PP
V
Symbol
SS1
V
SS1
Main supply voltage (
Digital circuit ground (0V) There are multiple V
connected
Reference for the A D converter (
analog portion of the A D converter and the logic used to read Port 0 Must be
connected for A D and Port 0 to function
Programming voltage for the OTPROM parts It should be
It is also the timing pin for the return from powerdown circuit Connect to V
powerdown not being used
Reference ground for the A D converter Must be held at nominally the same
potential as V
Input of the oscillator inverter and the internal clock generator
Output of the oscillator inverter
Output of the internal clock generator The frequency is
It has a 50% duty cycle Also LSIO pin
Reset input to and open-drain output from the chip RESET has an internal pullup
Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin
dyamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low
an 8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ‘‘0’’
and CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is
‘‘0’’ all bus cycles are 16-bit CCR bit 1
an LSIO pin when not used as BUSWIDTH
A positive transition causes a non maskable interrupt vector through memory
location 203EH
Output high during an external memory read indicates the read is an instruction
fetch INST is valid throughout the bus cycle INST is active only during external
memory fetches during internal OTPROM fetches INST is held low Also LSIO when
not INST SLPCS is the Slave Port Chip Select
Input for memory select (External Access) EA equal to a high causes memory
accesses to locations 0FF2000H through 0FF9FFFH to be directed to on-chip
OTPROM EA equal to a low causes accesses to these locations to be directed to
off-chip memory EA
Mode EA is latched at reset
Bus Hold Input requesting control of the bus
Bus Hold acknowledge output indicating release of the bus
Bus Request output activated when the bus controller has a pending external
memory cycle
Address Latch Enable or Address Valid output as selected by CCR Both pin
options provide a latch to demultiplex the address from the address data bus When
the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used
as a chip select for external memory ALE ADV is active only during external
memory accesses Also LSIO when not used as ALE SLPADDR is the Slave Port
Address Control Input and SLPALE is the Slave Port Address Latch Enable Input
Read signal output to external memory RD is active only during external memory
reads or LSIO when not used as RD SLPRD is the Slave Port Read Control Input
SS
e a
a
5V)
12 5V causes execution to begin in the Programming
Name and Function
a
5V) V
e
REF
‘‘0’’ and CCR1 bit 2
SS
is also the supply voltage to the
pins all of which MUST be
a
the oscillator frequency
12 5V for programming
e
‘‘0’’ is illegal Also
8XC196NT
CC
if
5