P89C662HFA/00,512 NXP Semiconductors, P89C662HFA/00,512 Datasheet - Page 50

• Manufacturer Part Number: P89C662HFA/00,512
• Description: IC 80C51 MCU FLASH 32K 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89C662HFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 568-1270-5; 935267446512; P89C662HFA

1. L = Level activated
2. T = Transition activated
Philips Semiconductors
Interrupt Priority Structure
The P89C660/662/664/668 has an 8 source four-level interrupt
structure (see Table 13).
There are 4 SFRs associated with the four-level interrupt. They are
the IE, IP, IEN1, and IPH (see Figures 35, 36, 37, and 38). The IPH
(Interrupt Priority High) register makes the four-level interrupt
structure possible. The IPH is located at SFR address B7H. The
structure of the IPH register and a description of its bits is shown in
Figure 37.
The function of the IPH SFR, when combined with the IP SFR,
determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 13.
NOTES:
2002 Oct 28
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
IPH.x
PRIORITY BITS
0
0
1
1
SI01 (I
SOURCE
BIT
IEN0.7
IEN0.6
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
PCA
SP
X0
T0
X1
T1
T2
IEN0 (0A8H)
Interrupt Table
2
C)
IP.x
0
1
0
1
SYMBOL
EA
EC
ES1
ES0
ET1
EX1
ET0
EX0
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
INTERRUPT PRIORITY LEVEL
INTERRUPT PRIORITY LEVEL
POLLING PRIORITY
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
PCA interrupt enable bit
I
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
EA
2
7
C interrupt enable bit.
1
2
3
4
5
6
7
8
EC
6
ES1
5
Figure 35. IE Registers
REQUEST BITS
ES0
4
TF2, EXF2
CF, CCFn
n = 0–4
RI, TI
TP0
TF1
IE0
IE1
—
50
ET1
3
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except that there are four interrupt levels rather than
two (as on the 80C51). An interrupt will be serviced as long as an
interrupt of equal or higher priority is not already being serviced. If
an interrupt of equal or higher level priority is being serviced, the
new interrupt will wait until it is finished before being serviced. If a
lower priority level interrupt is being serviced, it will be stopped and
the new interrupt serviced. When the new interrupt is finished, the
lower priority level interrupt that was stopped will be completed.
EX1
2
P89C660/P89C662/P89C664/
HARDWARE CLEAR?
N (L)
ET0
N (L) Y (T)
1
1
N
Y
Y
N
N
N
Y (T)
EX0
0
2
VECTOR ADDRESS
P89C668
SU01454
2BH
0BH
1BH
3BH
03H
13H
23H
33H
Product data