P89C662HFA/00,512 NXP Semiconductors, P89C662HFA/00,512 Datasheet - Page 16

• Manufacturer Part Number: P89C662HFA/00,512
• Description: IC 80C51 MCU FLASH 32K 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89C662HFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 568-1270-5; 935267446512; P89C662HFA

Philips Semiconductors
Serial Clock Generator
This programmable clock pulse generator provides the SCL clock
pulses when SIO1 is in the Master Transmitter or Master Receiver
mode. It is switched off when SIO1 is in a Slave mode. The
programmable output clock frequencies are: f
(12-clock mode) or f
Timer 1 overflow rate divided by eight. The output clock pulses have
a 50% duty cycle unless the clock generator is synchronized with
other SCL clock sources as described above.
Timing and Control
The timing and control logic generates the timing and control signals
for serial byte handling. This logic block provides the shift pulses for
S1DAT, enables the comparator, generates and detects start and
stop conditions, receives and transmits acknowledge bits, controls
the master and Slave modes, contains interrupt request logic, and
monitors the I
Control Register, S1CON
This 7-bit special function register is used by the microcontroller to
control the following SIO1 functions: start and restart of a serial
transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
Status Decoder and Status Register
The status decoder takes all of the internal status bits and
compresses them into a 5-bit code. This code is unique for each I
bus status. The 5-bit code may be used to generate vector
addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26
possible bus states if all four modes of SIO1 are used. The 5-bit
status code is latched into the five most significant bits of the status
register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The
three least significant bits of the status register are always zero. If
the status code is used as a vector to service routines, then the
routines are displaced by eight address locations. Eight bytes of
code is sufficient for most of the service routines.
The Four SIO1 Special Function Registers
The microcontroller interfaces to SIO1 via four special function
registers. These four SFRs (S1ADR, S1DAT, S1CON, and S1STA)
are described individually in the following sections.
The Address Register, S1ADR
The CPU can read from and write to this 8-bit, directly addressable
SFR. S1ADR is not affected by the SIO1 hardware. The contents of
this register are irrelevant when SIO1 is in a Master mode. In the
Slave modes, the seven most significant bits must be loaded with
the microcontroller’s own slave address, and, if the least significant
bit is set, the general call address (00H) is recognized; otherwise it
is ignored.
The most significant bit corresponds to the first bit received from the
I
high level on the I
on the bus.
The Data Register, S1DAT
S1DAT contains a byte of serial data to be transmitted or a byte
which has just been received. The CPU can read from and write to
2002 Oct 28
2
S1ADR (DBH)
C bus after a start condition. A logic 1 in S1ADR corresponds to a
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2
C bus status.
7
X
2
C bus, and a logic 0 corresponds to a low level
OSC
6
X
/60, f
5
X
OSC
own slave address
/4800 (6-clock mode) and the
4
X
3
X
OSC
/120, f
2
X
OSC
1
X
/9600
GC
0
2
C
16
when a serial interrupt is requested, and the STO bit is cleared when
this 8-bit, directly addressable SFR while it is not in the process of
shifting a byte. This occurs when SIO1 is in a defined state and the
serial interrupt flag is set. Data in S1DAT remains stable as long as
SI is set. Data in S1DAT is always shifted from right to left: the first
bit to be transmitted is the MSB (bit 7), and, after a byte has been
received, the first bit of received data is located at the MSB of
S1DAT. While data is being shifted out, data on the bus is
simultaneously being shifted in; S1DAT always contains the last
data byte present on the bus. Thus, in the event of lost arbitration,
the transition from master transmitter to slave receiver is made with
the correct data in S1DAT.
SD7 - SD0:
Eight bits to be transmitted or just received. A logic 1 in S1DAT
corresponds to a high level on the I
corresponds to a low level on the bus. Serial data shifts through
S1DAT from right to left. Figure 6 shows how data in S1DAT is
serially transferred to and from the SDA line.
S1DAT and the ACK flag form a 9-bit shift register which shifts in or
shifts out an 8-bit byte, followed by an acknowledge bit. The ACK
flag is controlled by the SIO1 hardware and cannot be accessed by
the CPU. Serial data is shifted through the ACK flag into S1DAT on
the rising edges of serial clock pulses on the SCL line. When a byte
has been shifted into S1DAT, the serial data is available in S1DAT,
and the acknowledge bit is returned by the control logic during the
ninth clock pulse. Serial data is shifted out from S1DAT via a buffer
(BSD7) on the falling edges of clock pulses on the SCL line.
When the CPU writes to S1DAT, BSD7 is loaded with the content of
S1DAT.7, which is the first bit to be transmitted to the SDA line (see
Figure 7). After nine serial clock pulses, the eight bits in S1DAT will
have been transmitted to the SDA line, and the acknowledge bit will
be present in ACK. Note that the eight transmitted bits are shifted
back into S1DAT.
The Control Register, S1CON
The CPU can read from and write to this 8-bit, directly addressable
SFR. Two bits are affected by the SIO1 hardware: the SI bit is set
a STOP condition is present on the I
cleared when ENS1 = “0”.
S1CON (D8H)
ENS1, the SIO1 Enable Bit: ENS1 = “0”: When ENS1 is “0”, the
SDA and SCL outputs are in a high impedance state. SDA and SCL
input signals are ignored, SIO1 is in the “not addressed” slave state,
and the STO bit in S1CON is forced to “0”. No other bits are
affected. P1.6 and P1.7 may be used as open drain I/O ports.
ENS1 = “1”: When ENS1 is “1”, SIO1 is enabled. The P1.6 and P1.7
port latches must be set to logic 1.
ENS1 should not be used to temporarily release SIO1 from the I2C
bus since, when ENS1 is reset, the I2C bus status is lost. The AA
flag should be used instead (see description of the AA flag in the
following text).
S1DAT (DAH)
P89C660/P89C662/P89C664/
CR2
SD7
7
7
SD6
ENS1
6
6
SD5
5
STA
5
shift direction
SD4
2
4
C bus, and a logic 0
2
STO
C bus. The STO bit is also
4
SD3
3
SI
3
P89C668
SD2
AA
2
2
CR1
Product data
SD1
1
1
SD0
CR0
0
0