PIC12F635-E/MF Microchip Technology, PIC12F635-E/MF Datasheet - Page 31

• Manufacturer Part Number: PIC12F635-E/MF
• Description: IC MCU FLASH 1KX14 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-E/MF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNAC162057 - MPLAB ICD 2 HEADER 14DIPXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

2.2.2.4
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
EEIE
PIC16F636/639 only.
PIE1 Register
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enables the LVD interrupt
0 = Disables the LVD interrupt
CRIE: Cryptographic Interrupt Enable bit
1 = Enables the cryptographic interrupt
0 = Disables the cryptographic interrupt
C2IE: Comparator 2 Interrupt Enable bit
1 = Enables the Comparator 2 interrupt
0 = Disables the Comparator 2 interrupt
C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the oscillator fail interrupt
0 = Disables the oscillator fail interrupt
Unimplemented: Read as ‘0’
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
R/W-0
LVDIE
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
W = Writable bit
‘1’ = Bit is set
R/W-0
CRIE
C2IE
R/W-0
PIC12F635/PIC16F636/639
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
C1IE
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
OSFIE
R/W-0
x = Bit is unknown
U-0
—
DS41232D-page 29
TMR1IE
R/W-0
bit 0