PIC12F635-E/MF Microchip Technology, PIC12F635-E/MF Datasheet - Page 105

• Manufacturer Part Number: PIC12F635-E/MF
• Description: IC MCU FLASH 1KX14 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-E/MF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNAC162057 - MPLAB ICD 2 HEADER 14DIPXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

PIC12F635/PIC16F636/639
11.15 Configurable Output Enable Filter
The purpose of this filter is to enable the LFDATA output
and wake the microcontroller only after receiving a
specific sequence of pulses on the LC input pins.
Therefore, it prevents the AFE from waking up the
microcontroller due to noise or unwanted input signals.
The circuit compares the timing of the demodulated
header waveform with a pre-defined value, and enables
the demodulated LFDATA output when a match occurs.
The output enable filter consists of a high (T
) and
OEH
low duration (T
) of a pulse immediately after the
OEL
AGC settling gap time. The selection of high and low
times further implies a max period time. The output
enable high and low times are determined by SPI
interface programming. Figure 11-5 and Figure 11-6
show the output enable filter waveforms.
There should be no missing cycles during T
.
OEH
Missing cycles may result in failing the output enable
condition.
FIGURE 11-5:
OUTPUT ENABLE FILTER TIMING
Required Output Enable Sequence
Data Packet
T
STAB
(T
+ T
)
AGC
PAGC
Demodulator
T
GAP
Output
t
T
t
T
OEL
OEH
Start bit
AGC
AFE
Wake-up
Gap Pulse
LFDATA output is enabled
and AGC Stabilization
t
T
OET
on this rising edge
© 2007 Microchip Technology Inc.
DS41232D-page 103