AT90S8515-8JI Atmel, AT90S8515-8JI Datasheet - Page 20

• Manufacturer Part Number: AT90S8515-8JI
• Description: IC MCU 8K FLSH 8MHZ IT 44PLCC
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8515-8JI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Status Register – SREG
20
AT90S8515
Table 1. AT90S8515 I/O Space (Continued)
Note:
All AT90S8515 I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions transferring data between the 32 general-pur-
pose working registers and the I/O space. I/O registers within the address range $00 -
$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set section for more details. When using the I/O-specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as
SRAM, $20 must be added to this address. All I/O register addresses throughout this
document are shown with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The I/O and peripherals control registers are explained in the following sections.
The AVR status register (SREG) at I/O space location $3F ($5F) is defined as:
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable bit is cleared (zero), none of the interrupts are enabled indepen-
dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
Bit
$3F ($5F)
Read/Write
Initial Value
Address Hex
$0D ($2D)
$0C ($2C)
$0E ($2E)
$0B ($2B)
$0A ($2A)
$0F ($2F)
$11 ($31)
$10 ($30)
$09 ($29)
$08 ($28)
Reserved and unused locations are not shown in the table.
R/W
7
0
I
DDRD
SPDR
UBRR
Name
SPSR
SPCR
ACSR
PIND
UDR
USR
UCR
R/W
6
T
0
Function
Data Direction Register, Port D
Input Pins, Port D
SPI I/O Data Register
SPI Status Register
SPI Control Register
UART I/O Data Register
UART Status Register
UART Control Register
UART Baud Rate Register
Analog Comparator Control and Status Register
R/W
H
5
0
R/W
S
4
0
R/W
V
3
0
R/W
N
2
0
R/W
1
Z
0
R/W
C
0
0
0841G–09/01
SREG