PIC16C84-04I/SO Microchip Technology, PIC16C84-04I/SO Datasheet - Page 46

• Manufacturer Part Number: PIC16C84-04I/SO
• Description: IC MIC CTL EEPM 1K 4MHZ IT18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C84-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Data Converters: -
• Connectivity: -

PIC16C84
8.9.1
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
8.9.2
An overflow (FFh
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 6.0).
8.9.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 5.2).
EXAMPLE 8-1:
PUSH
ISR
POP
DS30445C-page 46
Note 1: If a change on an I/O pin should occur
MOVWF
SWAPF
MOVWF
:
:
:
:
SWAPF
MOVWF
SWAPF
INT INTERRUPT
TMR0 INTERRUPT
PORT RB INTERRUPT
SWAPF
on
when a read operation of PORTB is being
executed (start of the Q2 cycle), the RBIF
interrupt flag bit may not get set.
the
W_TEMP
STATUS, W
STATUS_TEMP
STATUS_TEMP, W
STATUS
W_TEMP, F
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP, W
00h) in TMR0 will set flag bit T0IF
RB0/INT
pin,
; Copy W to TEMP register,
; Swap status to be saved into W
; Save status to STATUS_TEMP register
:
; Interrupt Service Routine
;
;
; Swap nibbles in STATUS_TEMP register
; and place result into W
; Move W into STATUS register
;
; Swap nibbles in W_TEMP and place result in W_TEMP
the
should configure Bank as required
(sets bank to original state)
; Swap nibbles in W_TEMP and place result into W
INTF
bit
8.10
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and STATUS
register). This is implemented in software.
Example 8-1 stores and restores the STATUS and W
register’s values. The User defined registers, W_TEMP
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
Example 8-1 does the following:
a)
b)
c)
d)
e)
Stores the W register.
Stores the STATUS register in STATUS_TEMP.
Executes the Interrupt Service Routine code.
Restores the STATUS (and bank select bit)
register.
Restores the W register.
Context Saving During Interrupts
1997 Microchip Technology Inc.